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1.发明公开公开(公告)号：US20240171165A1
公开(公告)日：2024-05-23
申请号：US18383511
申请日：2023-10-25
Applicant: MEDIA TEK INC.
Inventor： Ahmed Safwat Mohamed Aboelenein Elmallah , Mohammed Mohsen Abdulsalam Abdullatif , Tamer Mohammed Ali
IPC: H03K5/1252 , H03M1/82
CPC classification number: H03K5/1252 , H03M1/82 , H03K2005/00058
Abstract: A circuit or reducing fractional spurs comprises a digital to time converter (DTC) comprising multiple delay stages electrically coupled to one another in series, configured such that each delay stage is binary switched till the code exceeds cell range and then it is fully turned ON, and thereafter it is moved to the next stage, each delay stage comprising a digitally controlled delay line (DCDL) having code-dependent integrated nonlinearity (INL), with the maximal value of the INL occuring at a mid-code position; and an offset stage comprising the DCDL electrically coupled to the DTC in series, configured to generate random codes for each required time delay of the DTC to ensure the probability of landing at the mid-code position is reduced and landing point is kept as far away as possible from the mid-code position for every required time delay, thereby improving the INL and the fractional spurs.
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公开(公告)号：US11990911B2
公开(公告)日：2024-05-21
申请号：US17654916
申请日：2022-03-15
Applicant: QUALCOMM Incorporated
Inventor： Negar Rashidi , Nitz Saputra , Ashok Swaminathan
CPC classification number: H03K5/05 , G06F1/08 , H03K5/156 , H03M1/0624 , H03M1/0836 , H03M1/1215 , H03M1/82
Abstract: In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.
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3.发明授权公开(公告)号：US11962314B2
公开(公告)日：2024-04-16
申请号：US17400851
申请日：2021-08-12
Applicant: SOCIONEXT INC.
Inventor： Kenichi Okada , Hanli Liu , Zheng Sun
CPC classification number: H03L7/0991 , G06F1/06 , G06F1/08 , H03K5/01 , H03M1/82 , H03K2005/00078
Abstract: With respect to a phase locked loop (PLL) circuit that receives a first reference clock and generates an output clock, the PLL circuit includes a delay circuit that delays the first reference clock to generate a second reference clock, a feedback circuit that generates a control signal based on a phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency determined based on the control signal to generate the output clock, and a divider that divides the output clock in the on state. The PLL circuit switches between a first mode and a second mode, the feedback clock in the first mode is a signal obtained by retiming an output of the divider with the output clock, and the feedback clock in the second mode is a signal obtained by retiming the first reference clock with the output clock.
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公开(公告)号：US11923857B1
公开(公告)日：2024-03-05
申请号：US18102066
申请日：2023-01-26
Applicant: XILINX, INC.
Inventor： Hongtao Zhang , Ankur Jain , Yanfei Chen , Ronan Sean Casey , Winson Lin , Hsung Jai Im
CPC classification number: H03L7/0802 , H03L7/0991 , H03M1/82
Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.
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公开(公告)号：US11923856B2
公开(公告)日：2024-03-05
申请号：US17713901
申请日：2022-04-05
Applicant: XILINX, INC.
Inventor： Bob W. Verbruggen , Christophe Erdmann
CPC classification number: H03K5/14 , H03K5/135 , H03K5/15066 , H03K19/0948 , H03M1/82 , H03K2005/00026
Abstract: Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.
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Patent Agency Ranking
公开(公告)号：US20230299757A1
公开(公告)日：2023-09-21
申请号：US17654916
申请日：2022-03-15
Applicant: QUALCOMM Incorporated
Inventor： Negar RASHIDI , Nitz SAPUTRA , Ashok SWAMINATHAN
Abstract: In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.
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公开(公告)号：US20180175878A1
公开(公告)日：2018-06-21
申请号：US15811721
申请日：2017-11-14
Applicant: Intel IP Corporation
Inventor： Ofir Degani , Rotem Banin , Assaf Ben-Bassat , Sebastian Sievert
CPC classification number: H03M1/82 , H03K5/131 , H03K5/135 , H03K2005/00052 , H03K2005/00058 , H03M1/007 , H04W88/02
Abstract: An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.
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公开(公告)号：US09985644B1
公开(公告)日：2018-05-29
申请号：US15872017
申请日：2018-01-16
Applicant: Realtek Semiconductor Corp.
Inventor： Yu Zhao , Chia-Liang (Leon) Lin
Abstract: A DTC (digital-to-time converter) includes: an inverter configured to receive an input clock at an input node and output an output clock at an output node, and a variable source degeneration network controlled by a digital word, wherein the inverter includes a transistor with a gate terminal connected to the input node, a drain terminal coupled to the output node, and a source terminal connected to the variable source degeneration network, and the variable source degeneration network includes a parallel connection of a resistor and a digitally-controlled capacitor of a capacitance controlled by the digital word.
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公开(公告)号：US09859913B2
公开(公告)日：2018-01-02
申请号：US14871980
申请日：2015-09-30
Applicant: Synaptics Incorporated
Inventor： Marshall Bell , Stephen Morein , Imre Knausz
CPC classification number: H03M1/66 , G09G3/20 , G09G5/18 , G09G2310/0259 , G09G2310/027 , G09G2320/0693 , G09G2330/12 , H03M1/1014 , H03M1/1057 , H03M1/82
Abstract: A source driver including: a current source that provides an approximately constant current; a channel coupled to a source electrode and including a digital to analog converters (DAC), the DAC including: a voltage source that applies an output voltage to the source electrode based on the approximately constant current provided by the current source; and a control unit having circuitry that: inputs a digital value; and terminates, based on the digital value, charging of the voltage source by the approximately constant current; and a calibration unit having circuitry that: generates a comparison between a test voltage applied by the voltage source with a target voltage; and modifies the approximately constant current based on the comparison.
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公开(公告)号：US09692443B2
公开(公告)日：2017-06-27
申请号：US14720155
申请日：2015-05-22
Applicant: Intel Deutschland GmbH
Inventor： Bernd-Ulrich Klepser , Markus Scholz , Zdravko Boos , Thomas Mayer
CPC classification number: H03M1/74 , H03M1/82 , H04L27/2003 , H04L27/361
Abstract: Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.
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