公开(公告)号：US11990911B2

公开(公告)日：2024-05-21

申请号：US17654916

申请日：2022-03-15

申请人： QUALCOMM Incorporated

发明人： Negar Rashidi ,  Nitz Saputra ,  Ashok Swaminathan

IPC分类号： H03K5/05 ,  G06F1/08 ,  H03K5/156 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H03M1/82

CPC分类号： H03K5/05 ,  G06F1/08 ,  H03K5/156 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215 ,  H03M1/82

摘要： In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.

公开(公告)号：US10516412B1

公开(公告)日：2019-12-24

申请号：US16138499

申请日：2018-09-21

申请人： QUALCOMM INCORPORATED

发明人： Shahin Mehdizad Taleie ,  Ashok Swaminathan ,  Sudharsan Kanagaraj ,  Negar Rashidi ,  Siyu Yang ,  Behnam Sedighi ,  Honghao Ji ,  Jaswinder Singh ,  Andrew Weil ,  Dongwon Seo ,  Xilin Liu

IPC分类号： H03M1/66 ,  G04F10/00 ,  H03M1/68

摘要： An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.

公开(公告)号：US11184018B1

公开(公告)日：2021-11-23

申请号：US17087234

申请日：2020-11-02

申请人： QUALCOMM Incorporated

发明人： Xilin Liu ,  Parisa Mahmoudidaryan ,  Shahin Mehdizad Taleie ,  Negar Rashidi ,  Dongwon Seo

IPC分类号： H03M1/18 ,  H03M1/82 ,  H03M1/06 ,  H03M1/10 ,  H03K5/156 ,  H03K5/05 ,  H03M1/80 ,  H03K5/00

摘要： Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.