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公开(公告)号：US11476841B2
公开(公告)日：2022-10-18
申请号：US17198515
申请日：2021-03-11
Applicant: QUALCOMM INCORPORATED
Inventor： Liang Dai , Kentaro Yamamoto , Behnam Sedighi
Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.
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公开(公告)号：US11569801B2
公开(公告)日：2023-01-31
申请号：US17198515
申请日：2021-03-11
Applicant: QUALCOMM INCORPORATED
Inventor： Liang Dai , Kentaro Yamamoto , Behnam Sedighi
Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.
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公开(公告)号：US11962317B2
公开(公告)日：2024-04-16
申请号：US17804779
申请日：2022-05-31
Applicant: QUALCOMM Incorporated
Inventor： Behnam Sedighi , Shi Bu , Elias Dagher , Dinesh Jagannath Alladi
IPC: H03M1/08
CPC classification number: H03M1/0854
Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.
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4.发明申请公开(公告)号：US20200099389A1
公开(公告)日：2020-03-26
申请号：US16367712
申请日：2019-03-28
Applicant: QUALCOMM Incorporated
Inventor： Eunyung Sung , Nitz Saputra , Behnam Sedighi , Ashok Swaminathan , Honghao Ji , Shahin Mehdizad Taleie , Dongwon Seo
Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.
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公开(公告)号：US10454487B1
公开(公告)日：2019-10-22
申请号：US16118019
申请日：2018-08-30
Applicant: Qualcomm Incorporated
Inventor： Behnam Sedighi , Andrew Weil , Nitz Saputra
Abstract: The present disclosure describes aspects of segmented resistor architecture for digital-to-analog converters (DACs). In some aspects, a DAC circuit is implemented with a first resistor network coupled to a set of binary code-controlled current sources and a second resistor network that includes a resistor coupled between the first resistor network and an output of the DAC circuit. A set of thermometer code-controlled current sources are coupled to a node of the second resistor network and provide varying amounts of current. This current is scaled based on a resistance of the second resistor network's resistor, which is higher than a resistance of the first resistor network and effective to increase a combined output impedance of the first and second resistor networks. The increase of output impedance reduces noise of the resistor networks that transfers to the output of the DAC circuit, thereby improving signal-to-noise performance of the DAC circuit.
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Patent Agency Ranking
公开(公告)号：US12261621B2
公开(公告)日：2025-03-25
申请号：US17949149
申请日：2022-09-20
Applicant: QUALCOMM Incorporated
Inventor： Behnam Sedighi
Abstract: Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.
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公开(公告)号：US11901909B2
公开(公告)日：2024-02-13
申请号：US17664358
申请日：2022-05-20
Applicant: QUALCOMM Incorporated
Inventor： Igor Gutman , Behnam Sedighi , Tao Luo , Elias Dagher , Jeremy Darren Dunworth
IPC: H03M1/18
Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.
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公开(公告)号：US20220294433A1
公开(公告)日：2022-09-15
申请号：US17198515
申请日：2021-03-11
Applicant: QUALCOMM INCORPORATED
Inventor： Liang Dai , Kentaro Yamamoto , Behnam Sedighi
Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.
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公开(公告)号：US10516412B1
公开(公告)日：2019-12-24
申请号：US16138499
申请日：2018-09-21
Applicant: QUALCOMM INCORPORATED
Inventor： Shahin Mehdizad Taleie , Ashok Swaminathan , Sudharsan Kanagaraj , Negar Rashidi , Siyu Yang , Behnam Sedighi , Honghao Ji , Jaswinder Singh , Andrew Weil , Dongwon Seo , Xilin Liu
Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.
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公开(公告)号：US10305361B2
公开(公告)日：2019-05-28
申请号：US15710704
申请日：2017-09-20
Applicant: QUALCOMM Incorporated
Inventor： Nitz Saputra , Sang Min Lee , Dongwon Seo , Vinay Kundur , Behnam Sedighi , Honghao Ji
Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.
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