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    Digital-to-analog converter (DAC) with common-mode correction
    1.
    发明授权
    Digital-to-analog converter (DAC) with common-mode correction 有权

    公开(公告)号：US11271576B1

    公开(公告)日：2022-03-08

    申请号：US17223559

    申请日：2021-04-06

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew Weil ,  Ashok Swaminathan ,  Siyu Yang

    IPC: H03M1/10

    Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of current-steering cells, each having a bypass switch, and a resistor ladder circuit having multiple segments. Each segment may include a first resistive element and a second resistive element, the bypass switch being configured to selectively provide a bypass current to a common node between the first resistive element and the second resistive element.

    Digital-to-analog converter (DAC) design with reduced settling time
    3.
    发明授权
    Digital-to-analog converter (DAC) design with reduced settling time 有权

    公开(公告)号：US10461768B1

    公开(公告)日：2019-10-29

    申请号：US16208724

    申请日：2018-12-04

    Applicant: QUALCOMM Incorporated

    Inventor： Zongyu Dong ,  Andrew Weil ,  Dongwon Seo

    IPC: H03M1/66 ,  H03M1/80 ,  H03M1/06

    Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of transistors selectively coupled to an output of the DAC, and a biasing circuit coupled to gates of the plurality of transistors. The biasing circuit may include a first transistor having a gate coupled to a drain of the first transistor, a first buffer having an input coupled to the gate of the first transistor, a second transistor having a gate coupled to an output of the first buffer, a first resistive-capacitive (RC) circuit having a first resistive element and a first capacitive element, the first RC circuit being coupled between the gate of the first transistor and the gate of the second transistor, and a first switch coupled between the first resistive element and the first capacitive element.

    Low headroom cascode bias circuit for cascode current mirrors
    4.
    发明授权
    Low headroom cascode bias circuit for cascode current mirrors 有权

    公开(公告)号：US12228956B2

    公开(公告)日：2025-02-18

    申请号：US17982420

    申请日：2022-11-07

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew Weil

    IPC: G05F3/26

    Abstract: A cascode bias circuit biases a gate of a cascode transistor in a cascode current mirror. The cascode bias circuit includes a first transistor configured to conduct a first current and includes a second transistor configured to conduct a second current. The first and second transistors couple to a third transistor configured to conduct a sum of the first current and the second current. A gate of the first transistor couples to a gate of the cascode transistor to bias the cascode transistor.

    Compact frequency-locked loop architecture for digital clocking
    5.
    发明授权
    Compact frequency-locked loop architecture for digital clocking 有权

    公开(公告)号：US12261612B2

    公开(公告)日：2025-03-25

    申请号：US18177445

    申请日：2023-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： John Abcarius ,  Debesh Bhatta ,  Andrew Weil ,  Robert Martin Ondris ,  Wenjing Yin

    IPC: H03L7/099

    Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

    Segmented resistor architecture for digital-to-analog converters
    8.
    发明授权
    Segmented resistor architecture for digital-to-analog converters 有权

    公开(公告)号：US10454487B1

    公开(公告)日：2019-10-22

    申请号：US16118019

    申请日：2018-08-30

    Applicant: Qualcomm Incorporated

    Inventor： Behnam Sedighi ,  Andrew Weil ,  Nitz Saputra

    IPC: H03M1/08 ,  H04B1/16 ,  H04B1/04

    Abstract: The present disclosure describes aspects of segmented resistor architecture for digital-to-analog converters (DACs). In some aspects, a DAC circuit is implemented with a first resistor network coupled to a set of binary code-controlled current sources and a second resistor network that includes a resistor coupled between the first resistor network and an output of the DAC circuit. A set of thermometer code-controlled current sources are coupled to a node of the second resistor network and provide varying amounts of current. This current is scaled based on a resistance of the second resistor network's resistor, which is higher than a resistance of the first resistor network and effective to increase a combined output impedance of the first and second resistor networks. The increase of output impedance reduces noise of the resistor networks that transfers to the output of the DAC circuit, thereby improving signal-to-noise performance of the DAC circuit.

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