Multiplier-accumulator unit element with binary weighted charge transfer capacitors

    公开(公告)号:US12014152B2

    公开(公告)日:2024-06-18

    申请号:US17334816

    申请日:2021-05-31

    摘要: A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.

    Chip to chip network routing using DC bias and differential signaling

    公开(公告)号:US11689443B2

    公开(公告)日:2023-06-27

    申请号:US17334703

    申请日:2021-05-29

    IPC分类号: H04L45/02

    CPC分类号: H04L45/08

    摘要: A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.

    Interlayer exchange coupled adder

    公开(公告)号:US11641783B2

    公开(公告)日:2023-05-02

    申请号:US17114498

    申请日:2020-12-08

    摘要: An adder device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A set of regions are positioned on a top layer above a continuous bottom layer, and the regions excited with magnetization for A and not A, B and not B, and C and not C to form a sum and an inverse carry output magnetization.

    Efficient Storage of Blockchain in Embedded Device

    公开(公告)号:US20220417008A1

    公开(公告)日:2022-12-29

    申请号:US17359545

    申请日:2021-06-26

    IPC分类号: H04L9/08 H04L9/32

    摘要: A lightweight node in a decentralized network includes stores a blockchain with a plurality of blocks. The lightweight node adds blocks to the blockchain successively. A given block having a header and a body. The header includes a data merkle root generated as a root hash of a data merkle tree with one or more leaf nodes that are one or more hashes. A given hash being a hash of a combination of (1) a public key associated with a lightweight node of the decentralized network and (2) of a validity value associated with the public key indicating whether the public key is a valid public key. The data merkle root being insufficient for restoring the data merkle tree. But with a public key and an intermediate hash the date merkle root is sufficient for at least partly verifying the public key.

    Unit Element for Asynchronous Analog Multiplier Accumulator

    公开(公告)号:US20220207247A1

    公开(公告)日:2022-06-30

    申请号:US17139226

    申请日:2020-12-31

    IPC分类号: G06G7/16 G06F17/16 G06J1/00

    摘要: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

    Decompression engine for executable microcontroller code

    公开(公告)号:US10541708B1

    公开(公告)日:2020-01-21

    申请号:US16140526

    申请日:2018-09-24

    摘要: A code decompression engine reads compressed code from a memory containing a compressed code part and a dictionary part. The compressed code part contains a series of instructions being either an uncompressed instruction preceded by an uncompressed code bit, or a compressed instruction having a compressed code bit followed by a number of segments field followed by segments, followed by a directory index indication a directory location to read. Each segment consists of a mask type, a mask offset, and a mask.

    Encoder and decoder for transmission of coefficients to a neural network

    公开(公告)号:US10528641B2

    公开(公告)日:2020-01-07

    申请号:US15979257

    申请日:2018-05-14

    发明人: Jay A. Chesavage

    摘要: A method for efficient transmission of coefficients examines a coefficient list, presents the coefficients as binary floating point representation, and transmits the list of coefficients as a header having an exponent prefix, a fractional suffix, and each coefficient value as an exponent suffix and fractional prefix. A method for reception of coefficients receives a header including an exponent prefix, a fractional suffix, thereafter receiving each value as a sign bit, an exponent suffix and a fractional prefix, reconstituting an approximation of the original value, in sequence, as a sign bit, exponent prefix exponent suffix, fraction prefix, and fraction suffix, thereby greatly reducing the amount of information to be transmitted or received.

    Power-save system for detection of Bluetooth Long Range Packets

    公开(公告)号:US20190364504A1

    公开(公告)日:2019-11-28

    申请号:US16538797

    申请日:2019-08-12

    IPC分类号: H04W52/02 H04W4/80

    摘要: A preamble detector for a Bluetooth Long Range includes a receiver for forming baseband samples from Bluetooth packets and a preamble detect controller for enabling and disabling power to the receiver. Where the preamble duration is Tcyc, the preamble detector turns on for a preamble detect time T1 and turns off for a duration T2, where T2=Tcyc−2*T1. A series of hierarchical decisions is made on sequentially increasing intervals of time based on an accumulated correlation result of correlating the baseband samples against a SYNC sequence to power the receiver back down before the end of the T1 period when the accumulated correlation result is below a threshold and continues to a subsequent correlation interval when the accumulated correlation result is above a threshold, where the threshold is established to have at least a 20% false alarm rate for preamble detection.