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公开(公告)号：US20190364504A1
公开(公告)日：2019-11-28
申请号：US16538797
申请日：2019-08-12
摘要： A preamble detector for a Bluetooth Long Range includes a receiver for forming baseband samples from Bluetooth packets and a preamble detect controller for enabling and disabling power to the receiver. Where the preamble duration is Tcyc, the preamble detector turns on for a preamble detect time T1 and turns off for a duration T2, where T2=Tcyc−2*T1. A series of hierarchical decisions is made on sequentially increasing intervals of time based on an accumulated correlation result of correlating the baseband samples against a SYNC sequence to power the receiver back down before the end of the T1 period when the accumulated correlation result is below a threshold and continues to a subsequent correlation interval when the accumulated correlation result is above a threshold, where the threshold is established to have at least a 20% false alarm rate for preamble detection.
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公开(公告)号：US20190190765A1
公开(公告)日：2019-06-20
申请号：US16221368
申请日：2018-12-14
CPC分类号： H04L27/2692 , H04L27/0014 , H04L27/2613 , H04L2027/0095
摘要： A preamble detector for Bluetooth Low Energy includes a receiver for receiving Bluetooth packets and an energy detect controller for enabling power to the receiver during T1 and disabling power to the receiver during T2 in a cyclical fashion until an packet energy increase is detected followed by detection of a preamble. During the T1 interval an AGC process is operative which is also searching for an increase in energy from sample to sample within the same T1 interval, or across adjacent T1 intervals. If an energy increase is detected, a preamble detector is operative to determine if a preamble is present, and if the preamble is not present, the process resumes cycling through T1 and T2.
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3.发明申请公开(公告)号：US20210072906A1
公开(公告)日：2021-03-11
申请号：US16992098
申请日：2020-08-13
发明人： Subba Reddy KALLAM , Partha Sarathy MURALI , Venkata Siva Prasad PULAGAM , Anusha BIYYANI , Venkatesh VINJAMURI , Shahabuddin MOHAMMED , Rahul Kumar GURRAM , Akhil SONI
摘要： The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.
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公开(公告)号：US20190223102A1
公开(公告)日：2019-07-18
申请号：US16365133
申请日：2019-03-26
CPC分类号： H04W52/0229 , H04L1/0039 , H04W52/0216
摘要： A wireless receiver has a preamble detection apparatus and method which waits until the expected arrival of a beacon frame, after which power is cyclically applied during a preamble detection interval and a sleep interval until a preamble is detected. The preamble detector has a first mode with a longer preamble detection interval and a second mode with a shorter preamble detection interval. During the preamble detection interval, power is applied to receiver components, and during the sleep interval, power is not applied. The duration of the preamble detection interval is equal to a preamble sensing interval, and if a preamble is detected, power remains applied to a preamble processor for a preamble processing interval. The duration of the sleep interval is the duration of a long preamble less the sum of two times the preamble detection interval plus the preamble processing interval. Phase lock loop (PLL) power is applied a PLL settling time prior to and during the preamble detection interval.
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公开(公告)号：US20190191373A1
公开(公告)日：2019-06-20
申请号：US16221325
申请日：2018-12-14
发明人： Sriram MUDULODU , Partha Sarathy MURALI , SuryaNarayana Varma Nallaparaju , Logeshwaran VIJAYAN , Subba Reddy KALLAM , Venkat MATTELA
摘要： A wireless receiver powers up shortly before the expected arrival of a beacon frame, and upon detection of a beacon frame from an access point the station is associated with and determination of subsequent fields of interest, including at least a TIM field, the receiver powers down. At the previously identified fields of interest, the receiver powers up and uses previously stored values to continue packet demodulation, thereafter examining the TIM field to determine whether the AP has packets to transmit to the station.
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公开(公告)号：US20190129638A1
公开(公告)日：2019-05-02
申请号：US15794008
申请日：2017-10-26
发明人： Partha Sarathy MURALI , Venkata Siva Prasad Pulagam , Sailaja Dharani Naga SANKABATHULA , Venkat Rao Gunturu , Subba Reddy KALLAM
摘要： A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.
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公开(公告)号：US20190059055A1
公开(公告)日：2019-02-21
申请号：US15682541
申请日：2017-08-21
摘要： A wireless receiver has a preamble detection apparatus and method which waits until the expected arrival of a beacon frame, after which power is cyclically applied during a preamble detection interval and a sleep interval until a preamble is detected. The preamble detector has a first mode with a longer preamble detection interval and a second mode with a shorter preamble detection interval. During the preamble detection interval, power is applied to receiver components, and during the sleep interval, power is not applied. The duration of the preamble detection interval is equal to a preamble sensing interval, and if a preamble is detected, power remains applied to a preamble processor for a preamble processing interval. The duration of the sleep interval is the duration of a long preamble less the sum of two times the preamble detection interval plus the preamble processing interval. Phase lock loop (PLL) power is applied a PLL settling time prior to and during the preamble detection interval.
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公开(公告)号：US20210072995A1
公开(公告)日：2021-03-11
申请号：US16945936
申请日：2020-08-03
摘要： A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.
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公开(公告)号：US20190191374A1
公开(公告)日：2019-06-20
申请号：US16221561
申请日：2018-12-16
CPC分类号： H04W52/0229 , H04B7/00 , H04W4/80 , H04W84/12
摘要： A preamble detector for a Bluetooth Long Range includes a receiver for forming baseband samples from Bluetooth packets and a preamble detect controller for enabling and disabling power to the receiver. Where the preamble duration is Tcyc, the preamble detector turns on for a preamble detect time T1 and turns off for a duration T2, where T2=Tcyc−2*T1. A series of hierarchical decisions is made on sequentially increasing intervals of time based on an accumulated correlation result of correlating the baseband samples against a SYNC sequence to power the receiver back down before the end of the T1 period when the accumulated correlation result is below a threshold and continues to a subsequent correlation interval when the accumulated correlation result is above a threshold, where the threshold is established to have at least a 20% false alarm rate for preamble detection.
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10.发明申请公开(公告)号：US20190187745A1
公开(公告)日：2019-06-20
申请号：US16222858
申请日：2018-12-17
摘要： A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.
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