公开(公告)号：US20190129638A1

公开(公告)日：2019-05-02

申请号：US15794008

申请日：2017-10-26

申请人： Redpine Signals, Inc.

发明人： Partha Sarathy MURALI ,  Venkata Siva Prasad Pulagam ,  Sailaja Dharani Naga SANKABATHULA ,  Venkat Rao Gunturu ,  Subba Reddy KALLAM

IPC分类号： G06F3/06 ,  G06F13/40

摘要： A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.

公开(公告)号：US11307779B2

公开(公告)日：2022-04-19

申请号：US16992098

申请日：2020-08-13

申请人： Redpine Signals, Inc.

发明人： Subba Reddy Kallam ,  Partha Sarathy Murali ,  Venkata Siva Prasad Pulagam ,  Anusha Biyyani ,  Venkatesh Vinjamuri ,  Shahabuddin Mohammed ,  Rahul Kumar Gurram ,  Akhil Soni

IPC分类号： G06F3/06 ,  G06F12/06

摘要： The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

公开(公告)号：US11288072B2

公开(公告)日：2022-03-29

申请号：US16945936

申请日：2020-08-03

申请人： Redpine Signals, Inc.

发明人： Subba Reddy Kallam ,  Partha Sarathy Murali ,  Venkat Mattela ,  Venkata Siva Prasad Pulagam

IPC分类号： G06F9/38 ,  G06F9/52 ,  G06F9/30

摘要： A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.