公开(公告)号：US20180343014A1

公开(公告)日：2018-11-29

申请号：US15987099

申请日：2018-05-23

Applicant: Seiko Epson Corporation

Inventor： Masayoshi TODOROKIHARA

IPC: H03M3/00 ,  G01R23/00

CPC classification number: H03M3/372 ,  G01R23/005 ,  H03M3/30 ,  H03M3/3283 ,  H03M3/346 ,  H03M3/466 ,  H03M3/472

Abstract: An idle tone dispersion device outputs a frequency delta-sigma modulation signal obtained by using either one of a reference signal and a measured signal to perform frequency delta-sigma modulation of the other and dispersing an idle tone. The idle tone dispersion device includes n (n is any natural number equal to or larger than 2) frequency delta-sigma modulation sections and an adder configured to add up output signals of the n frequency delta-sigma modulation sections and output the frequency delta-sigma modulation signal. Each of the n frequency delta-sigma modulation sections uses either one of the reference signal and the measured signal to perform the frequency delta-sigma modulation of the other. At least one of the reference signal and the measured signal includes jitter including a frequency component higher than a frequency of an idle tone of an output signal of the frequency delta-sigma modulation section.

公开(公告)号：US20180062692A1

公开(公告)日：2018-03-01

申请号：US15614667

申请日：2017-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUN-HO HUH ,  HO-RANG JANG ,  SEOK-CHAN KIM ,  IN-TAE KANG ,  SANG-HEON LEE ,  KWAN-YEOB CHAE ,  JUNE-HEE LEE ,  SANG-HUNE PARK ,  JAE-CHOL LEE ,  HYUNG-KWEON LEE

IPC: H04B1/44 ,  H03M3/00 ,  H04L27/06 ,  H04L27/26

CPC classification number: H04B1/44 ,  H03M3/00 ,  H03M3/462 ,  H03M3/466 ,  H04L7/04 ,  H04L27/06 ,  H04L27/2655 ,  H04L27/2656

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

公开(公告)号：US09722626B2

公开(公告)日：2017-08-01

申请号：US14589484

申请日：2015-01-05

Applicant: General Electric Company

Inventor： Amit Satish Gore ,  Emad Andarawis Andarawis ,  Naresh Kesavan Rao

IPC: H03M3/00 ,  G01D5/22

CPC classification number: H03M3/35 ,  G01D5/2291 ,  H03M3/466

Abstract: An analog-to-digital converter (ADC) is provided includes a first sigma-delta modulator (SDM) electrically coupled to a first signal input. The first SDM includes a first summing junction configured to receive a plurality of inputs to the first SDM. The ADC further includes a second sigma-delta modulator (SDM) electrically coupled to a second signal input. The second SDM includes a second summing junction configured to receive a plurality of inputs to the second SDM. The first SDM also includes a cross-coupled feedback loop from an output of the first SDM to a negative input of the first summing junction and to a positive input of the second summing junction. The second SDM also includes a cross-coupled feedback loop from an output of the second SDM to a negative input of the first summing junction and to a negative input of the second summing junction.

公开(公告)号：US09442141B2

公开(公告)日：2016-09-13

申请号：US14150164

申请日：2014-01-08

Applicant: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.

Inventor： Gerald Miaille ,  Michael John Story ,  Dimitrios Mavridis

IPC: G01R23/02 ,  G01R23/00 ,  H03M3/00

CPC classification number: G01R23/00 ,  H03M3/42 ,  H03M3/44 ,  H03M3/454 ,  H03M3/466 ,  H03M3/47

Abstract: An analogue-to-digital converter for converting an analogue input signal into a digital output signal, the analogue-to-digital converter including two conversion paths, each configured to receive a version of the analogue input signal and convert it into a digital bit stream, a first feedback loop configured to provide feed-back, to both paths, that is indicative of a difference between the digital bit streams output by the two paths, and a second feedback loop configured to feed-back, to both paths, that is indicative of an average of the digital bit streams output by the two paths.

Abstract translation: 一种用于将模拟输入信号转换为数字输出信号的模拟 - 数字转换器，所述模数转换器包括两个转换路径，每个转换路径被配置为接收模拟输入信号的版本并将其转换成数字位流 第一反馈回路，其被配置为向两个路径提供表示由两个路径输出的数字位流之间的差异的反馈回路，以及被配置为反馈到两个路径的第二反馈回路， 指示由两条路径输出的数字比特流的平均值。

公开(公告)号：US09389252B2

公开(公告)日：2016-07-12

申请号：US14755850

申请日：2015-06-30

Applicant: Semtech Corporation

Inventor： Olivier Nys ,  Pascal Monney

IPC: G01R13/14 ,  G01R19/25 ,  G01R19/10 ,  G01R19/252 ,  H03M3/00

CPC classification number: G01R19/25 ,  G01R19/10 ,  G01R19/252 ,  H03K2217/960735 ,  H03M3/414 ,  H03M3/46 ,  H03M3/466

Abstract: A sampling circuitry for a plurality of electrodes the circuitry comprising a plurality of charge amplifiers and a plurality of modulators, wherein each charge amplifier and each modulator, comprised in the plurality of charge amplifiers and the plurality of modulators, respectively, corresponds to an electrode of the plurality of electrodes, wherein each modulator is capable of generating a residue signal and a rough code corresponding to each sampled electrode of the plurality of electrodes, a multiplexer capable of receiving a plurality of residue signals generated by the plurality of modulators, a residue analog to digital converter capable of receiving a multiplexed residue signal from the multiplexer and outputting a digitized multiplexed residue signal, and a digital summation circuitry capable of receiving the digitized multiplexed residue signal and a plurality of rough codes, comprising each rough code corresponding to each sample electrode, and outputting a plurality of output codes.

Abstract translation: 一种用于多个电极的采样电路，所述电路包括多个电荷放大器和多个调制器，其中分别包括在所述多个电荷放大器和所述多个调制器中的每个电荷放大器和每个调制器对应于 所述多个电极，其中每个调制器能够产生残留信号和对应于所述多个电极中的每个采样的电极的粗略码，多路复用器，其能够接收由所述多个调制器产生的多个残留信号;残差模拟 数字转换器，其能够从多路复用器接收多路复用的残留信号并输出​​数字化的多路复用残差信号;以及数字求和电路，其能够接收数字化多路复用残差信号和多个粗略码，包括对应于每个样本电极的每个粗略码 ，并输出多个outp ut代码。

公开(公告)号：US20150372699A1

公开(公告)日：2015-12-24

申请号：US14744246

申请日：2015-06-19

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： TIMOTHY J. TALTY ,  Zhiwei A. Xu ,  Mohiuddin Ahmed ,  Cynthia D. Baringer ,  Al Cosand ,  James Chingwei Li ,  Yen-Cheng Kuan ,  Peter Petre

IPC: H04B1/00 ,  H03M1/66 ,  H03M3/00

CPC classification number: H04B1/0003 ,  H03M3/338 ,  H03M3/408 ,  H03M3/466 ,  H03M3/502

Abstract: An RF transmitter module for a cellular radio that includes a delta-sigma modulator having a plurality of interleaving dynamic element matching (DEM) circuits providing interleaved digital bits at a reduced clock rate. An interleaver controller controls the DEM circuits so as to provide groups of the digital bits at different points in time. In one embodiment, a summation junction adds the groups of the digital bits to provide a continuous stream of the interleaved digital bits, a DAC converts the stream of interleaved digital bits to an analog signal, and a power amplifier amplifies the analog signal.

Abstract translation: 一种用于蜂窝无线电的RF发射机模块，其包括具有多个交织动态元素匹配（DEM）电路的delta-sigma调制器，以降低的时钟速率提供交织的数字比特。 交织器控制器控制DEM电路，以便在不同的时间点提供数字比特组。 在一个实施例中，加法结加上数字位组以提供交错数字位的连续流，DAC将交错数字位流转换为模拟信号，功率放大器放大模拟信号。

公开(公告)号：US09148164B1

公开(公告)日：2015-09-29

申请号：US14480343

申请日：2014-09-08

Applicant: Cirrus Logic, Inc.

Inventor： Edmund Mark Schneider ,  Aniruddha Satoskar ,  Daniel J. Allen ,  Seyedeh Maryam Mortazavi Zanjani

IPC: H03M1/12 ,  H03M1/18 ,  H03M1/00 ,  H03M1/06 ,  H03M3/00 ,  H04R3/04

CPC classification number: H04R3/02 ,  H03M1/002 ,  H03M1/0631 ,  H03M1/18 ,  H03M1/181 ,  H03M1/188 ,  H03M3/466 ,  H04R3/04 ,  H04R2420/01 ,  H04R2430/03

Abstract: A processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise and increase dynamic range. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.

公开(公告)号：US20130282384A1

公开(公告)日：2013-10-24

申请号：US13920549

申请日：2013-06-18

Applicant: Motorola Mobility LLC

Inventor： Jonathan A Gibbs

IPC: G10L19/00

CPC classification number: G10L19/12 ,  G10L19/00 ,  G10L19/008 ,  G10L19/032 ,  G10L19/06 ,  G10L19/087 ,  G10L19/24 ,  G10L25/06 ,  G10L25/12 ,  G10L25/18 ,  G10L25/21 ,  G10L25/24 ,  H03M3/466 ,  H04S2400/01 ,  H04S2420/03

Abstract: An encoding apparatus comprises a frame processor (105) which receives a multi channel audio signal comprising at least a first audio signal from a first microphone (101) and a second audio signal from a second microphone (103). An ITD processor 107 then determines an inter time difference between the first audio signal and the second audio signal and a set of delays (109, 111) generates a compensated multi channel audio signal from the multi channel audio signal by delaying at least one of the first and second audio signals in response to the inter time difference signal. A combiner (113) then generates a mono signal by combining channels of the compensated multi channel audio signal and a mono signal encoder (115) encodes the mono signal. The inter time difference may specifically be determined by an algorithm based on determining cross correlations between the first and second audio signals.

Abstract translation: 编码装置包括帧处理器（105），其接收包括来自第一麦克风（101）的至少第一音频信号和来自第二麦克风（103）的第二音频信号的多声道音频信号。 ITD处理器107然后确定第一音频信号和第二音频信号之间的时间差，并且一组延迟（109,111）通过延迟多声道音频信号中的至少一个从多声道音频信号产生经补偿的多声道音频信号 响应于时间差信号的第一和第二音频信号。 组合器（113）然后通过组合经补偿的多声道音频信号的信道和对单声道信号进行编码的单声道信号编码器（115）来产生单声道信号。 时间差可以具体地通过基于确定第一和第二音频信号之间的互相关的算法来确定。

公开(公告)号：US07796076B2

公开(公告)日：2010-09-14

申请号：US12037932

申请日：2008-02-26

Applicant: John L. Melanson

Inventor： John L. Melanson

IPC: H03M1/12

CPC classification number: H03M3/41 ,  G01R31/2844 ,  H03K17/0822 ,  H03K17/691 ,  H03M3/466

Abstract: A transformer-isolated analog-to-digital converter (ADC) feedback apparatus and method provides reduction of circuit complexity in high power/high voltage systems having a transformer-isolated sensing circuit. The feedback apparatus is a circuit including an ADC for receiving an analog input signal and a transformer having a first winding that receives a modulated output of the analog-to-digital converter. A second winding of the transformer provides an isolated data output of the ADC. A demodulator is coupled to the second winding of the transformer and demodulates the isolated output to generate a digital representation of the analog input signal. The ADC may be a delta-sigma converter and the demodulator may be the corresponding decimation filter. The circuit further includes an isolation circuit for introducing a clock signal and/or power supply waveform at the second winding of the transformer, so that the ADC circuit is supplied with an isolated clock and/or an isolated power supply.

Abstract translation: 变压器隔离的模数转换器（ADC）反馈装置和方法提供具有变压器隔离感测电路的大功率/高压系统中的电路复杂性的降低。 反馈装置是包括用于接收模拟输入信号的ADC和具有接收模拟 - 数字转换器的调制输出的第一绕组的变压器的电路。 变压器的第二个绕组提供了ADC的隔离数据输出。 解调器耦合到变压器的第二绕组，并解调隔离输出以产生模拟输入信号的数字表示。 ADC可以是Δ-Σ转换器，并且解调器可以是相应的抽取滤波器。 电路还包括用于在变压器的第二绕组处引入时钟信号和/或电源波形的隔离电路，使得ADC电路被提供有隔离时钟和/或隔离电源。

公开(公告)号：US06657574B1

公开(公告)日：2003-12-02

申请号：US10314555

申请日：2002-12-09

Applicant: Jason Powell Rhode

Inventor： Jason Powell Rhode

IPC: H03M112

CPC classification number: H03M3/466 ,  H03M1/1205

Abstract: An analog-to-digital converter is provided for converting multiple analog inputs into corresponding digital values. An output interface circuit uses differential signaling to reduce noise and interference induced in the analog portions of the analog-to-digital converter.

Abstract translation: 提供了一个模拟 - 数字转换器，用于将多个模拟输入转换为相应的数字值。 输出接口电路使用差分信令来减少在模数转换器的模拟部分中引起的噪声和干扰。