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    PULSE WIDTH MODULATION DATA RECOVERY DEVICE AND DRIVING METHOD THEREOF
    4.
    发明申请
    PULSE WIDTH MODULATION DATA RECOVERY DEVICE AND DRIVING METHOD THEREOF 有权
    脉冲宽度调制数据恢复装置及其驱动方法

    公开(公告)号：US20160013957A1

    公开(公告)日：2016-01-14

    申请号：US14710713

    申请日：2015-05-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JUNE-HEE LEE ,  JUN-HAN BAE ,  BONG-KYU KIM ,  JONG-JAE RUY

    IPC: H04L25/49 ,  H04L7/033 ,  H04L25/02

    CPC classification number: H04L25/4902 ,  H04L7/0331 ,  H04L25/0272

    Abstract: A pulse width modulation (PWM) data recovery device includes a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal including a differential positive data signal and a differential negative data signal, and an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data in synchronization with a reference clock.

    Abstract translation: 脉冲宽度调制（PWM）数据恢复装置包括差分到单（DTS）电路，其被配置为使用包括差分正数据信号和差分负数据信号的差分数据信号产生PWM位，以及配置 通过检测同步模式来激活位锁定信号，通过与差分正数据信号和差分负数据信号之一同步地接收PWM位来恢复符号数据，并且与参考时钟同步地发送符号数据。

    EQUALIZER AND TRANSMITTER INCLUDING THE SAME
    5.
    发明申请
    EQUALIZER AND TRANSMITTER INCLUDING THE SAME 有权

    公开(公告)号：US20210344328A1

    公开(公告)日：2021-11-04

    申请号：US17372744

    申请日：2021-07-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： GUN-IL KANG ,  JUNE-HEE LEE ,  BYUNG-WOOK CHO

    IPC: H03H17/06 ,  H03H17/02 ,  H04L27/01

    Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

    DATA INTERFACE AND DATA TRANSMISSION METHOD
    7.
    发明申请
    DATA INTERFACE AND DATA TRANSMISSION METHOD 有权
    数据接口和数据传输方法

    公开(公告)号：US20160116936A1

    公开(公告)日：2016-04-28

    申请号：US14623069

    申请日：2015-02-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNG-KYUN JEONG ,  JUNG-HOON CHUN ,  JUNE-HEE LEE ,  WON-HO CHOI

    IPC: G06F1/08 ,  G06F13/40

    CPC classification number: G06F1/08 ,  G06F13/4068

    Abstract: A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.

    Abstract translation: 数据接口包括对第一位组采样的第一采样器和对第二位组采样的第二采样器。 第一位组包括包括在第一图像数据中的第一位和包括在第二图像中的第三位，并且第二位组包括第二位，其包括在第一图像数据中并且是高位位 比第一位和第四位包含在第二图像数据中并且是高于第三位的高位位。 数据接口还包括时钟发生器，其被配置为基于多相时钟调整第一和第二位组的采样定时，以及由第一采样器共享的时钟数据恢复（CDR）电路，第二采样器并被配置为输出 多相时钟到时钟发生器。

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