公开(公告)号：US20160116936A1

公开(公告)日：2016-04-28

申请号：US14623069

申请日：2015-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-KYUN JEONG ,  JUNG-HOON CHUN ,  JUNE-HEE LEE ,  WON-HO CHOI

IPC: G06F1/08 ,  G06F13/40

CPC classification number: G06F1/08 ,  G06F13/4068

Abstract: A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.

Abstract translation: 数据接口包括对第一位组采样的第一采样器和对第二位组采样的第二采样器。 第一位组包括包括在第一图像数据中的第一位和包括在第二图像中的第三位，并且第二位组包括第二位，其包括在第一图像数据中并且是高位位 比第一位和第四位包含在第二图像数据中并且是高于第三位的高位位。 数据接口还包括时钟发生器，其被配置为基于多相时钟调整第一和第二位组的采样定时，以及由第一采样器共享的时钟数据恢复（CDR）电路，第二采样器并被配置为输出 多相时钟到时钟发生器。

公开(公告)号：US20150340070A1

公开(公告)日：2015-11-26

申请号：US14819978

申请日：2015-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WUN-KI JUNG ,  MIN-HO KWON ,  KWI-SUNG YOO ,  WON-HO CHOI ,  DONG-HUN LEE ,  SEOG-HEON HAM

IPC: G11C7/06 ,  G11C7/10 ,  H01L27/146 ,  G11C7/22

CPC classification number: G11C7/06 ,  G11C7/10 ,  G11C7/1033 ,  G11C7/1051 ,  G11C7/22 ,  G11C19/00 ,  G11C27/02 ,  H01L27/146 ,  H01L27/14634 ,  H01L27/14643

Abstract: A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

Abstract translation: 行存储器件包括多个存储单元，数据线对，读出放大器和输出单元。 多个存储单元被一行地相邻配置。 数据线对耦合到存储器单元以将存储在存储器单元中的存储器数据位顺序传送到读出放大器。 读出放大器被配置为放大通过数据线对顺序传送的存储器数据位，相应的延迟时间彼此不同。 输出单元对读出放大器的输出进行采样，以响应读取的时钟信号顺序地输出存储器数据位的重新定时数据位。 读取时钟信号具有小于延迟时间之间的最大延迟时间的循环周期。

公开(公告)号：US20130228672A1

公开(公告)日：2013-09-05

申请号：US13757977

申请日：2013-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WUN-KI JUNG ,  MIN-HO KWON ,  KWI-SUNG YOO ,  WON-HO CHOI ,  DONG-HUN LEE ,  SEOG-HEON HAM

IPC: G11C7/06 ,  H01L27/146 ,  G11C7/10

CPC classification number: G11C7/06 ,  G11C7/10 ,  G11C7/1033 ,  G11C7/1051 ,  G11C7/22 ,  G11C19/00 ,  G11C27/02 ,  H01L27/146 ,  H01L27/14634 ,  H01L27/14643

Abstract: A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.