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1.
公开(公告)号:US20180323820A1
公开(公告)日:2018-11-08
申请号:US16037024
申请日:2018-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JUN-HO HUH , HO-RANG JANG , SEOK-CHAN KIM , IN-TAE KANG , SANG-HEON LEE , KWAN-YEOB CHAE , JUNE-HEE LEE , SANG-HUNE PARK , JAE-CHOL LEE , HYUNG-KWEON LEE
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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2.
公开(公告)号:US20200036409A1
公开(公告)日:2020-01-30
申请号:US16592525
申请日:2019-10-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JUN-HO HUH , HO-RANG JANG , SEOK-CHAN KIM , IN-TAE KANG , SANG-HEON LEE , KWAN-YEOB CHAE , JUNE-HEE LEE , SANG-HUNE PARK , JAE-CHOL LEE , HYUNG-KWEON LEE
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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3.
公开(公告)号:US20190207620A1
公开(公告)日:2019-07-04
申请号:US16186761
申请日:2018-11-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SANG-HEON LEE , MICHAEL CHOI
Abstract: An analog-digital converter has multiple feedback, and includes: a capacitor digital-analog converter including a plurality of switches driven by a digital code, and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code; first and second feedback capacitors each storing the residue voltage; an integrator configured to generate an integral signal by integrating the residue voltage; first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion interval, and the digital output signal corresponding to an average of first and second digital control signals during a delta sigma analog-digital conversion interval, wherein the first and second comparison signals are respectively fed back to the first and second feedback capacitors. The analog-digital converter may be included in various electronic devices, including communication devices.
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4.
公开(公告)号:US20180062692A1
公开(公告)日:2018-03-01
申请号:US15614667
申请日:2017-06-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JUN-HO HUH , HO-RANG JANG , SEOK-CHAN KIM , IN-TAE KANG , SANG-HEON LEE , KWAN-YEOB CHAE , JUNE-HEE LEE , SANG-HUNE PARK , JAE-CHOL LEE , HYUNG-KWEON LEE
CPC classification number: H04B1/44 , H03M3/00 , H03M3/462 , H03M3/466 , H04L7/04 , H04L27/06 , H04L27/2655 , H04L27/2656
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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