公开(公告)号：US12206431B2

公开(公告)日：2025-01-21

申请号：US18119311

申请日：2023-03-09

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang ,  Wei-Cian Hong

IPC: H03M1/12 ,  H03M1/46 ,  H03H19/00

Abstract: A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.

公开(公告)号：US12184170B2

公开(公告)日：2024-12-31

申请号：US18086720

申请日：2022-12-22

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang ,  Wei-Cian Hong

IPC: H02M3/07 ,  H03K5/24

Abstract: A comparator-based switched-capacitor circuit has a first output terminal and a second output terminal, and includes a switch-capacitor network, a first current source, and a second current source. Each of the first current source and the second current source includes a first transistor, a second transistor, a capacitor, and a buffer circuit. The first transistor has a first source, a first drain, and a first gate. The first drain is coupled to the first output terminal, the first source is coupled to a reference voltage, and the first gate is coupled to the switch-capacitor network. The second transistor has a second source, a second drain, and a second gate. The second source is coupled to the first output terminal. The capacitor is coupled between the second gate and the second source. The buffer circuit is coupled between the second source and the second drain.

公开(公告)号：US12052027B2

公开(公告)日：2024-07-30

申请号：US17946072

申请日：2022-09-16

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Wei-Cian Hong

IPC: H03M1/34 ,  H03M1/46 ,  H03M1/80 ,  H03M1/82

CPC classification number: H03M1/34 ,  H03M1/466 ,  H03M1/80 ,  H03M1/804 ,  H03M1/82

Abstract: The present invention discloses an analog-to-digital conversion circuit having speed-up comparison mechanism. Each of a positive and a negative capacitor arrays receives a positive and a negative input voltages to generate a positive and a negative output voltages. A first comparator performs comparison thereon to generate a first comparison result and a second comparator performs comparison according to a reference voltage to generate a second comparison result. A control circuit switches a capacitor enabling combination of the capacitor arrays according to the first comparison result and outputs a digital code as a digital output signal when the positive and the negative output voltages equal. The control circuit operates in a speed-up switching mode when a difference between the positive and the negative output voltages is outside of a predetermined range defined by the reference voltage and operates in a normal switching mode when the difference is within the predetermined range.

公开(公告)号：US12143118B2

公开(公告)日：2024-11-12

申请号：US17864471

申请日：2022-07-14

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang ,  Yen-Ting Wu ,  Wei-Cian Hong

IPC: H03M1/12

Abstract: A front-end sampling circuit includes a global switch, a local switch, and an auxiliary switch. The global switch is configured to be selectively turned on according to a first control signal, in order to transmit an input signal. The local switch is configured to be selectively turned on according to a second control signal, in order to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is configured to be selectively turned on according to a third control signal, in order to transmit the input signal to the node, in which a turn-off time point of the auxiliary switch is set to be the same or earlier than a turn-off time point of the global switch.

公开(公告)号：US12107597B2

公开(公告)日：2024-10-01

申请号：US17857621

申请日：2022-07-05

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang ,  Wei-Cian Hong ,  Sheng-Yen Shih

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/468 ,  H03M1/1245

Abstract: A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.

公开(公告)号：US12126353B2

公开(公告)日：2024-10-22

申请号：US17945136

申请日：2022-09-15

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Wei-Cian Hong

IPC: H03M1/34 ,  H03M1/08 ,  H03M1/46

CPC classification number: H03M1/34 ,  H03M1/0863 ,  H03M1/462 ,  H03M1/468

Abstract: The present invention discloses an analog-to-digital conversion circuit having quick tracking mechanism is provided. A positive and a negative capacitor arrays receive a positive and a negative input voltages and output a positive and a negative output voltages. A first and a second comparators performs comparison thereon respectively according to and not according to a reference voltage to generate a first and a second comparison results. A control circuit does not perform level-shifting when a difference between the positive and the negative output voltages is not within a predetermined range. The control circuit assigns the positive and the negative capacitor arrays a voltage up-tracking direction and a voltage down-tracking direction respectively to switch a capacitor enabling combination with digital codes according to the second comparison result, and outputs the digital codes as a digital output signal when the positive and the negative output voltages equal.

公开(公告)号：US12113544B2

公开(公告)日：2024-10-08

申请号：US17864464

申请日：2022-07-14

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Sheng-Yen Shih ,  Shih-Hsiung Huang ,  Wei-Cian Hong

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/38 ,  H03M3/04

CPC classification number: H03M1/38 ,  H03M1/1245 ,  H03M3/04

Abstract: A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.

公开(公告)号：US12068755B2

公开(公告)日：2024-08-20

申请号：US17944340

申请日：2022-09-14

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang ,  Wei-Cian Hong ,  Sheng-Yen Shih

IPC: H03M1/80 ,  H03M1/56 ,  H03M1/74 ,  H03M1/82

CPC classification number: H03M1/804 ,  H03M1/56 ,  H03M1/742 ,  H03M1/825

Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.