公开(公告)号：US20220224348A1

公开(公告)日：2022-07-14

申请号：US17461997

申请日：2021-08-31

申请人： Texas Instruments Incorporated

发明人： Michael Henderson Perrott ,  Hon Kin Chiu

IPC分类号： H03M1/08 ,  H03M1/06 ,  H03M1/18 ,  G11C11/4099 ,  G11C11/4093

摘要： In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

公开(公告)号：US20240146311A1

公开(公告)日：2024-05-02

申请号：US18404055

申请日：2024-01-04

申请人： Texas Instruments Incorporated

发明人： Michael Henderson Perrott ,  Hon Kin Chiu

IPC分类号： H03L7/08 ,  G11C11/4093 ,  G11C11/4099 ,  H03L7/04 ,  H03L7/081 ,  H03L7/107 ,  H03L7/187 ,  H03M1/06 ,  H03M1/08 ,  H03M1/18

CPC分类号： H03L7/0807 ,  G11C11/4093 ,  G11C11/4099 ,  H03L7/04 ,  H03L7/0816 ,  H03L7/1072 ,  H03L7/187 ,  H03M1/0626 ,  H03M1/0687 ,  H03M1/0836 ,  H03M1/182

摘要： In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.

公开(公告)号：US11870446B2

公开(公告)日：2024-01-09

申请号：US17461997

申请日：2021-08-31

申请人： Texas Instruments Incorporated

发明人： Michael Henderson Perrott ,  Hon Kin Chiu

IPC分类号： H03M1/12 ,  H03L7/08 ,  H03L7/107 ,  H03L7/081 ,  H03L7/187 ,  H03L7/04 ,  G11C11/4093 ,  G11C11/4099 ,  H03M1/06 ,  H03M1/08 ,  H03M1/18

CPC分类号： H03L7/0807 ,  G11C11/4093 ,  G11C11/4099 ,  H03L7/04 ,  H03L7/0816 ,  H03L7/1072 ,  H03L7/187 ,  H03M1/0626 ,  H03M1/0687 ,  H03M1/0836 ,  H03M1/182

摘要： In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.