公开(公告)号：US20240154324A1

公开(公告)日：2024-05-09

申请号：US18549356

申请日：2021-06-24

申请人： Intel Corporation

发明人： Sreenivas KASTURI ,  Xi LI ,  Gregory CHANCE ,  Wayne BALLANTYNE ,  Bruce GEREN ,  Peter PAWLIUK ,  Nebil TANZI

IPC分类号： H01Q25/00 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q21/08 ,  H01Q21/28

CPC分类号： H01Q25/002 ,  H01Q1/2266 ,  H01Q1/243 ,  H01Q21/08 ,  H01Q21/28

摘要： Disclosed herein are antenna systems, methods, and devices. The device includes a first portion including a first antenna array; and a second portion including a second antenna array, wherein the first portion and the second portion are movable with respect to one another, and wherein the first antenna array and the second antenna array are arranged such that in a first relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate in combination with one another, and in a second relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate independently of one another.

公开(公告)号：US20240172131A1

公开(公告)日：2024-05-23

申请号：US18548914

申请日：2021-06-25

申请人： Intel Corporation

发明人： Wayne BALLANTYNE ,  Chuanzhao YU ,  Ali AZAM ,  Gregory CHANCE ,  Lichung Tony CHANG

IPC分类号： H04W52/34 ,  H04L5/00 ,  H04W72/044 ,  H04W72/1273

CPC分类号： H04W52/34 ,  H04L5/0048 ,  H04W72/0473 ,  H04W72/1273

摘要： Methods and devices configured to determine, for a slot including a plurality of symbols allocated for downlink data, a downlink data block allocation scheme with a number of blocks of downlink data that remain constant or monotonically decrease starting at a designated symbol of the plurality of symbols allocated for downlink data; generate a voltage profile corresponding to the downlink data block allocation scheme, where the voltage profile includes a plurality of bias voltages; and apply a bias voltage selected from the plurality of bias voltages to a power amplifier in a transmission chain of the base station.

公开(公告)号：US20240235595A1

公开(公告)日：2024-07-11

申请号：US18477566

申请日：2023-09-29

申请人： Intel Corporation

发明人： Peter PAWLIUK ,  Gregory CHANCE

IPC分类号： H04B1/10

CPC分类号： H04B1/1027

摘要： A radio frequency front end device includes an antenna interface, configured to receive a signal representing a radio transmission; a radio frequency detector, wherein the signal includes a first signal in a first frequency range and a second signal in a second frequency range, adjacent to the first frequency range, and wherein the radio frequency detector is configured to detect the second signal within the second frequency range; and a processor, configured to select, based on the second signal, a sampling window size for a sampling window of a signal windowing procedure for the first signal in the first frequency range; and implement the signal windowing procedure on the first signal at the sampling window size.

公开(公告)号：US20240007070A1

公开(公告)日：2024-01-04

申请号：US17809908

申请日：2022-06-30

申请人： Intel Corporation

发明人： Gregory CHANCE ,  Peter PAWLIUK

IPC分类号： H03G3/30 ,  H03M1/18

CPC分类号： H03G3/3068 ,  H03M1/18 ,  H03G3/3089

摘要： A method and apparatus for automatic gain control (AGC). A transceiver includes an analog-to-digital converter (ADC) configured to convert a received analog signal to digital signal, a measurement circuitry configured to measure a signal level on the digital signal, an AGC controller configured to generate, based on the measured signal level, an analog gain control signal to change a gain to be applied to a received analog signal in analog domain and a digital gain control signal for digital gain compensation corresponding to the gain change in analog domain, and a digital gain compensation circuitry configured to apply the digital gain compensation based on the digital gain control signal. The digital compensation gain applied to the digital bits follows a ramp profile that is an inverse of a transient response to the gain change in analog domain.

公开(公告)号：US20180358406A1

公开(公告)日：2018-12-13

申请号：US15778603

申请日：2015-12-24

申请人： INTEL CORPORATION

发明人： Bruce A. BLOCK ,  Paul B. FISCHER ,  Nebil TANZI ,  Gregory CHANCE ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC分类号： H01L27/20 ,  H03H9/17 ,  H03H3/02 ,  H03H9/56 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

摘要： Techniques to fabricate an RF filter using 3 dimensional island integration are described. A donor wafer assembly may have a substrate with a first and second side. A first side of a resonator layer, which may include a plurality of resonator circuits, may be coupled to the first side of the substrate. A weak adhesive layer may be coupled to the second side of the resonator layer, followed by a low-temperature oxide layer and a carrier wafer. A cavity in the first side of the resonator layer may expose an electrode of the first resonator circuit. An RF assembly may have an RF wafer having a first and a second side, where the first side may have an oxide mesa coupled to an oxide layer. A first resonator circuit may be then coupled to the oxide mesa of the first side of the RF wafer.