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公开(公告)号：US11811416B2
公开(公告)日：2023-11-07
申请号：US17550493
申请日：2021-12-14
发明人： Kyu-hyoun Kim , Mingu Kang , Ankur Agrawal , Monodeep Kar
CPC分类号： H03M1/002
摘要： An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.
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公开(公告)号：US11770130B2
公开(公告)日：2023-09-26
申请号：US16808708
申请日：2020-03-04
发明人： Mingu Kang , Seyoung Kim , Seonghoon Woo
CPC分类号： H03M1/466
摘要： A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.
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公开(公告)号：US11853715B2
公开(公告)日：2023-12-26
申请号：US17101605
申请日：2020-11-23
发明人： Mingu Kang , Seonghoon Woo , Eun Kyung Lee
CPC分类号： G06F7/483 , G06F7/5443 , G06N3/04 , G06N3/08
摘要： A system comprises a floating-point computation unit configured to perform a dot-product operation in accordance with a first floating-point value and a second floating-point value, and detection logic operatively coupled to the floating-point computation unit. The detection logic is configured to compute a difference between fixed-point summations of exponent parts of the first floating-point value and the second floating-point value and, based on the computed difference, detect the presence of a condition prior to completion of the dot-product operation by the floating-point computation unit. In response to detection of the presence of the condition, the detection logic is further configured to cause the floating-point computation unit to avoid performing a subset of computations otherwise performed as part of the dot-product operation. Such techniques serve as a predictor that the avoided subset of computations would have resulted in a dot product of the two floating-point values being below a threshold value.
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公开(公告)号：US11562235B2
公开(公告)日：2023-01-24
申请号：US16797587
申请日：2020-02-21
发明人： Mingu Kang , Kyu-Hyoun Kim , Seyoung Kim , Chia-Yu Chen
摘要： A computer-implemented method for improving the efficiency of computing an activation function in a neural network system includes initializing, by a controller, weights in a weight vector associated with the neural network system. Further, the method includes receiving, by the controller, an input vector of input values for computing a dot product with the weight vector for the activation function, which determines an output value of a node in the neural network system. The method further includes predicting, by a rectifier linear unit (ReLU), which computes the activation function, that the output value of the node will be negative based on computing an intermediate value for computing the dot product, and based on a magnitude of the intermediate value exceeding a precomputed threshold value. Further, the method includes, in response to the prediction, terminating, by the ReLU, the computation of the dot product, and outputting a 0 as the output value.
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公开(公告)号：US20230083270A1
公开(公告)日：2023-03-16
申请号：US17474843
申请日：2021-09-14
发明人： Ankur Agrawal , Mingu Kang , Kyu-hyoun Kim , Monodeep Kar
摘要： An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform, with a first accuracy, a first portion of a bitwise multiplication of first and second digital inputs and to perform, with a second accuracy different than the first accuracy, at least a second portion of the bitwise multiplication.
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公开(公告)号：US11586912B2
公开(公告)日：2023-02-21
申请号：US16657263
申请日：2019-10-18
发明人： Chia-Yu Chen , Pin-Yu Chen , Mingu Kang , Jintao Zhang
摘要： Methods, systems, and circuits for training a neural network include applying noise to a set of training data across wordlines using a respective noise switch on each wordline. A neural network is trained using the noise-applied training data to generate a classifier that is robust against adversarial training.
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公开(公告)号：US20220359617A1
公开(公告)日：2022-11-10
申请号：US17308499
申请日：2021-05-05
发明人： Seonghoon Woo , Seyoung Kim , Mingu Kang
摘要： A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.
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公开(公告)号：US20220164163A1
公开(公告)日：2022-05-26
申请号：US17101605
申请日：2020-11-23
发明人： Mingu Kang , Seonghoon Woo , Eun Kyung Lee
摘要： A system comprises a floating-point computation unit configured to perform a dot-product operation in accordance with a first floating-point value and a second floating-point value, and detection logic operatively coupled to the floating-point computation unit. The detection logic is configured to compute a difference between fixed-point summations of exponent parts of the first floating-point value and the second floating-point value and, based on the computed difference, detect the presence of a condition prior to completion of the dot-product operation by the floating-point computation unit. In response to detection of the presence of the condition, the detection logic is further configured to cause the floating-point computation unit to avoid performing a subset of computations otherwise performed as part of the dot-product operation. Such techniques serve as a predictor that the avoided subset of computations would have resulted in a dot product of the two floating-point values being below a threshold value.
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9.发明授权公开(公告)号：US11314483B2
公开(公告)日：2022-04-26
申请号：US16737440
申请日：2020-01-08
发明人： Mingu Kang , Seyoung Kim , Kyu-hyoun Kim , Eun Kyung Lee
摘要： A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.
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公开(公告)号：US11301211B2
公开(公告)日：2022-04-12
申请号：US16847505
申请日：2020-04-13
发明人： Seyoung Kim , Mingu Kang , Kyu-hyoun Kim , Seonghoon Woo
摘要： A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
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