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公开(公告)号：US11770130B2
公开(公告)日：2023-09-26
申请号：US16808708
申请日：2020-03-04
发明人： Mingu Kang , Seyoung Kim , Seonghoon Woo
CPC分类号： H03M1/466
摘要： A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.
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公开(公告)号：US11853715B2
公开(公告)日：2023-12-26
申请号：US17101605
申请日：2020-11-23
发明人： Mingu Kang , Seonghoon Woo , Eun Kyung Lee
CPC分类号： G06F7/483 , G06F7/5443 , G06N3/04 , G06N3/08
摘要： A system comprises a floating-point computation unit configured to perform a dot-product operation in accordance with a first floating-point value and a second floating-point value, and detection logic operatively coupled to the floating-point computation unit. The detection logic is configured to compute a difference between fixed-point summations of exponent parts of the first floating-point value and the second floating-point value and, based on the computed difference, detect the presence of a condition prior to completion of the dot-product operation by the floating-point computation unit. In response to detection of the presence of the condition, the detection logic is further configured to cause the floating-point computation unit to avoid performing a subset of computations otherwise performed as part of the dot-product operation. Such techniques serve as a predictor that the avoided subset of computations would have resulted in a dot product of the two floating-point values being below a threshold value.
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3.发明授权公开(公告)号：US11302372B2
公开(公告)日：2022-04-12
申请号：US16785238
申请日：2020-02-07
摘要： A top pinned magnetic tunnel junction (MTJ) stack containing a magnetic pinned layered structure including a second magnetic pinned layer having strong perpendicular magnetic anisotropy (PMA) is provided. In the present application, the magnetic pinned layered structure includes a crystal grain growth controlling layer located between a first magnetic pinned layer having a body centered cubic (BCC) texture and the second magnetic pinned layer. The presence of the crystal grain growth controlling layer facilitates formation of a second magnetic pinned layer having a face centered cubic (FCC) texture or a hexagonal closed packing (HCP) texture which, in turn, promotes strong PMA to the second magnetic pinned layer of the magnetic pinned layered structure.
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公开(公告)号：US20220359617A1
公开(公告)日：2022-11-10
申请号：US17308499
申请日：2021-05-05
发明人： Seonghoon Woo , Seyoung Kim , Mingu Kang
摘要： A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.
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公开(公告)号：US20220164163A1
公开(公告)日：2022-05-26
申请号：US17101605
申请日：2020-11-23
发明人： Mingu Kang , Seonghoon Woo , Eun Kyung Lee
摘要： A system comprises a floating-point computation unit configured to perform a dot-product operation in accordance with a first floating-point value and a second floating-point value, and detection logic operatively coupled to the floating-point computation unit. The detection logic is configured to compute a difference between fixed-point summations of exponent parts of the first floating-point value and the second floating-point value and, based on the computed difference, detect the presence of a condition prior to completion of the dot-product operation by the floating-point computation unit. In response to detection of the presence of the condition, the detection logic is further configured to cause the floating-point computation unit to avoid performing a subset of computations otherwise performed as part of the dot-product operation. Such techniques serve as a predictor that the avoided subset of computations would have resulted in a dot product of the two floating-point values being below a threshold value.
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公开(公告)号：US11301211B2
公开(公告)日：2022-04-12
申请号：US16847505
申请日：2020-04-13
发明人： Seyoung Kim , Mingu Kang , Kyu-hyoun Kim , Seonghoon Woo
摘要： A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
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公开(公告)号：US12112242B2
公开(公告)日：2024-10-08
申请号：US16986506
申请日：2020-08-06
发明人： Mingu Kang , Seonghoon Woo , Eun Kyung Lee , Sukjay Chey
摘要： Techniques for performing improved machine learning using decision trees are disclosed. In one example, a system includes a plurality of decision tree structures, and configuration logic operatively coupled to the plurality of decision tree structures. The configuration logic selectively configures the plurality of decision tree structures to form at least one of: one or more combined decision tree structures, wherein a combined decision tree structure comprises multiple interconnected ones of the plurality of decision tree structures; and one or more individual decision tree structures, wherein an individual decision tree structure comprises a single one of the plurality of decision tree structures.
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公开(公告)号：US11793002B2
公开(公告)日：2023-10-17
申请号：US17308499
申请日：2021-05-05
发明人： Seonghoon Woo , Seyoung Kim , Mingu Kang
CPC分类号： H10B63/30 , G11C11/1673 , G11C11/1675 , H10N50/10 , H10N50/85
摘要： A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.
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公开(公告)号：US20220300797A1
公开(公告)日：2022-09-22
申请号：US17203705
申请日：2021-03-16
发明人： Seyoung Kim , Eun Kyung Lee , Mingu Kang , Seonghoon Woo
IPC分类号： G06N3/063 , G06N3/04 , G06N3/08 , G11C11/4063
摘要： An electronic circuit includes word lines; bit lines intersecting the word lines at a plurality of grid points; and resistive processing units located at the grid points. Baseline stochastic pulse input units are coupled to the word lines; differential stochastic pulse input units are coupled to the word lines; and bitline stochastic pulse input units are coupled to the bit lines. Control circuitry coupled to the pulse input units is configured to cause each of the baseline stochastic pulse input units to generate a baseline pulse train using base input data, each of the differential stochastic pulse input units to generate a differential pulse train using differential input data defining differences from the base input data, and each of the bitline stochastic pulse input units to generate a bitline pulse train using bit line input data. Neural network weights can thus be stored in the resistive processing units.
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公开(公告)号：US20210318852A1
公开(公告)日：2021-10-14
申请号：US16847505
申请日：2020-04-13
发明人： Seyoung Kim , Mingu Kang , Kyu-hyoun Kim , Seonghoon Woo
摘要： A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
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