公开(公告)号：US12101096B2

公开(公告)日：2024-09-24

申请号：US17182339

申请日：2021-02-23

申请人： Texas Instruments Incorporated

发明人： Prasanth K ,  Eeshan Miglani ,  Visvesvaraya Appala Pentakota ,  Kartik Goel ,  Jagannathan Venkataraman ,  Sai Aditya Krishnaswamy Nurani

IPC分类号： H03M1/10 ,  H03K5/24 ,  H03M1/00 ,  H03M1/06

CPC分类号： H03M1/0612 ,  H03K5/2481 ,  H03M1/002 ,  H03M1/1057

摘要： A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.