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公开(公告)号：US12101096B2
公开(公告)日：2024-09-24
申请号：US17182339
申请日：2021-02-23
发明人： Prasanth K , Eeshan Miglani , Visvesvaraya Appala Pentakota , Kartik Goel , Jagannathan Venkataraman , Sai Aditya Krishnaswamy Nurani
CPC分类号： H03M1/0612 , H03K5/2481 , H03M1/002 , H03M1/1057
摘要： A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.
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公开(公告)号：US20230138266A1
公开(公告)日：2023-05-04
申请号：US17515041
申请日：2021-10-29
IPC分类号： H03M1/10
摘要： An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a second multiplexer input and a second residue output, the second multiplexer input coupled to the second amplifier output.
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公开(公告)号：US20220209782A1
公开(公告)日：2022-06-30
申请号：US17133745
申请日：2020-12-24
发明人： Narasimhan RAJAGOPAL , Chirag Chandrahas SHETTY , Neeraj SHRIVASTAVA , Prasanth K , Eeshan MIGLANI
摘要： A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.
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公开(公告)号：US11881867B2
公开(公告)日：2024-01-23
申请号：US17467561
申请日：2021-09-07
发明人： Narasimhan Rajagopal , Eeshan Miglani , Chirag Chandrahas Shetty , Neeraj Shrivastava , Shagun Dusad , Srinivas Kumar Reddy Naru , Nithin Gopinath , Charls Babu , Shivam Srivastava , Viswanathan Nagarajan , Jagannathan Venkataraman , Harshit Moondra , Prasanth K , Visvesvaraya Appala Pentakota
IPC分类号： H03M1/10
CPC分类号： H03M1/1019
摘要： In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.
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公开(公告)号：US11689210B2
公开(公告)日：2023-06-27
申请号：US17515041
申请日：2021-10-29
IPC分类号： H03M1/10
CPC分类号： H03M1/1009
摘要： An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a second multiplexer input and a second residue output, the second multiplexer input coupled to the second amplifier output.
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6.发明公开公开(公告)号：US20240213998A1
公开(公告)日：2024-06-27
申请号：US18129604
申请日：2023-03-31
发明人： Rajashekar Goroju , Prasanth K , Dileepkumar Ramesh Bhat , Rakul Viswanath , Sravana Kumar Goli , Rahul Sharma
IPC分类号： H03M1/38
CPC分类号： H03M1/38
摘要： An example apparatus includes: controller circuitry configured to: provide switch signals to capacitive digital to analog converter (C-DAC) circuitry, the C-DAC circuitry including switches; configuring the switches into a third configuration begin an Auto Zero (AZ) phase with a third switch in a closed state; configuring the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to a first configuration; configuring the switches into a fifth configuration to repeat the transition of a first switch and a second switch to the open state corresponding to a second configuration; configuring the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to a second configuration; and performing an AZ decision with the switches in the sixth configuration.
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7.发明公开公开(公告)号：US20240072817A1
公开(公告)日：2024-02-29
申请号：US17899149
申请日：2022-08-30
发明人： Prasanth K , Rahul Sharma
CPC分类号： H03M1/0609 , H03M1/1023
摘要： An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.
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公开(公告)号：US11438001B2
公开(公告)日：2022-09-06
申请号：US17133745
申请日：2020-12-24
发明人： Narasimhan Rajagopal , Chirag Chandrahas Shetty , Neeraj Shrivastava , Prasanth K , Eeshan Miglani
摘要： A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.
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公开(公告)号：US20220271764A1
公开(公告)日：2022-08-25
申请号：US17182339
申请日：2021-02-23
发明人： Prasanth K , Eeshan MIGLANI , Visvesvaraya Appala PENTAKOTA , Kartik GOEL , Jagannathan VENKATARAMAN , Sai Aditya Krishnaswamy NURANI
摘要： A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.
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公开(公告)号：US20210328595A1
公开(公告)日：2021-10-21
申请号：US16850597
申请日：2020-04-16
发明人： Sai Aditya Krishnaswamy NURANI , Joseph Palackal MATHEW , Prasanth K , Visvesvaraya Appala PENTAKOTA , Shagun DUSAD
摘要： A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.
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