公开(公告)号：US11716090B2

公开(公告)日：2023-08-01

申请号：US17870831

申请日：2022-07-22

申请人： AyDeeKay LLC

发明人： Christopher A. Menkus ,  Robert W. Kim

IPC分类号： H03M1/06

CPC分类号： H03M1/0609 ,  H03M1/0612

摘要： An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

公开(公告)号：US10009038B2

公开(公告)日：2018-06-26

申请号：US15507704

申请日：2015-09-02

申请人： University of Southern California

发明人： Shuo-Wei Chen

IPC分类号： H03M1/12 ,  H03M1/14 ,  H03M1/50 ,  H03M1/06 ,  H03M1/10 ,  H03M1/60

CPC分类号： H03M1/1245 ,  H03M1/0609 ,  H03M1/10 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

摘要： An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

公开(公告)号：US20170284825A1

公开(公告)日：2017-10-05

申请号：US15628057

申请日：2017-06-20

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： John Paul LESSO ,  Emmanuel Philippe Christian HARDY ,  James Thomas DEAS ,  Toru IDO

IPC分类号： H04R3/06 ,  G01D5/24 ,  G01D5/244 ,  G01P15/125 ,  H03M1/06 ,  H03M3/00 ,  H04R19/00 ,  H04R19/04 ,  G01D3/02 ,  G01P15/08 ,  H03M1/12 ,  H04R29/00

CPC分类号： H04R3/06 ,  G01D3/02 ,  G01D5/24 ,  G01D5/24476 ,  G01P15/125 ,  G01P2015/0865 ,  H03M1/0609 ,  H03M1/12 ,  H03M3/352 ,  H03M3/458 ,  H04R19/005 ,  H04R19/04 ,  H04R29/004 ,  H04R2201/003 ,  H04R2499/11

摘要： This application relates to circuitry for processing sense signals generated by MEMS capacitive transducers for compensating for distortion in such sense signals. The circuitry has a signal path between an input (204) for receiving the sense signal and an output (205) for outputting an output signal based on said sense signal. Compensation circuitry (206, 207) is configured to monitor the signal at a first point along the signal path and generate a correction signal (Scorr); and modify the signal at at least a second point along said signal path based on said correction signal. The correction signal is generated as a function of the value of the signal at the first point along the signal path so as to introduce compensation components into the output signal that compensate for distortion components in the sense signal. The first point in the signal path may be before or after the second point in the signal path. The monitoring may be performed in an analogue or a digital part of the signal path and in either case the modification may be applied in an analogue or a digital part of the signal path.

公开(公告)号：US20170244422A1

公开(公告)日：2017-08-24

申请号：US15590563

申请日：2017-05-09

申请人： CANON KABUSHIKI KAISHA

发明人： Seiji Hashimoto ,  Takeru Suzuki ,  Yasushi Matsuno ,  Takashi Muto

IPC分类号： H03M1/06 ,  H03M1/12 ,  H04N5/335 ,  H03M1/56 ,  H04N5/225 ,  H03M1/10 ,  H03M1/18

CPC分类号： H03M1/0609 ,  H03M1/1019 ,  H03M1/123 ,  H03M1/186 ,  H03M1/56 ,  H04N5/225 ,  H04N5/3355 ,  H04N5/378

摘要： When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.

公开(公告)号：US20160359497A1

公开(公告)日：2016-12-08

申请号：US14732700

申请日：2015-06-06

申请人： Silicon Laboratories Inc.

发明人： Axel Thomsen ,  Alan L. Westwick

IPC分类号： H03M1/06 ,  H03M1/68 ,  H03M1/00 ,  H03M1/66

CPC分类号： H03M1/0607 ,  H03K5/003 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/66 ,  H03M1/664 ,  H03M1/682 ,  H03M1/747 ,  H03M1/808

摘要： Apparatus and associated methods are disclosed for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a decoder to decode the digital input signal and to provide first and second sets of control signals. The DAC also includes a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.

摘要翻译： 公开了用于具有改进的性能的数模转换的装置和相关方法。 在一个示例性实施例中，装置包括将数字输入信号转换为模拟输出信号的DAC。 DAC包括解码器以解码数字输入信号并提供第一和第二组控制信号。 DAC还包括电阻DAC（RDAC），以响应于第一组控制信号来提供第一和第二电压。 DAC还包括内插器，其被耦合以接收第一和第二电压并且响应于第二组控制信号而提供第一模拟信号。

公开(公告)号：US09362931B2

公开(公告)日：2016-06-07

申请号：US14750242

申请日：2015-06-25

申请人： Renesas Electronics Corporation

发明人： Takaya Yamamoto ,  Hideo Nakane ,  Keisuke Kimura ,  Yuichi Okuda ,  Takashi Oshima

IPC分类号： H03M1/12 ,  H03M1/00 ,  H03M1/06 ,  H03M1/46 ,  H03M1/10

CPC分类号： H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/124 ,  H03M1/145 ,  H03M1/38 ,  H03M1/462 ,  H03M1/468

摘要： There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.

摘要翻译： 提供了一种使用低功率和小面积的半导体器件，可以实现高精度的校准。 根据实施例的半导体器件包括A / D转换单元和耦合到A / D转换单元的输入侧的保持信号产生电路，并且具有不少于A / D转换单元的两个周期的保持周期， D转换单元。 保持信号生成电路包括：SC积分器，包括耦合到A / D转换单元的输入侧的输入缓冲器，以及耦合到输入缓冲器的输入和输出的反馈电容器; 以及将从A / D转换单元输出的多个比特的输出信号与第一和第二阈值进行比较的逻辑电路，并根据比较结果输出控制SC积分器的极性的控制信号。

公开(公告)号：US09154033B2

公开(公告)日：2015-10-06

申请号：US14130688

申请日：2012-07-03

申请人： Kenichi Hoshino ,  Teppei Hirotsu ,  Ryosuke Ishida

发明人： Kenichi Hoshino ,  Teppei Hirotsu ,  Ryosuke Ishida

IPC分类号： H03M1/14 ,  H02M3/157 ,  H03M1/06 ,  H03M1/12 ,  F02D41/20

CPC分类号： H02M3/157 ,  F02D2041/2024 ,  F02D2041/2058 ,  H03M1/0609 ,  H03M1/12

摘要： A current control semiconductor device that can detect a current with high precision within an IC of one chip by dynamically correcting a variation in a gain a and an offset b, and a control device using the semiconductor device are provided. A transistor 4, a current-voltage converter circuit 22, and an AD converter 23 are disposed on an identical semiconductor chip. Reference current generator circuits 6 and 6′ superimpose a current pulse Ic on a current of a load 2, and vary a voltage digital value output by the AD converter. A gain/offset correction unit 8 subjects a variation in a voltage digital value caused by the reference current generator circuits 6, 6′ to signal processing, and dynamically acquires gains a, a′ and offsets b, b′ in a linear relational expression of the voltage digital value output by the AD converter 23 and a current digital value of the load. A current digital value calculation unit 12 corrects a voltage value output by the AD converter with the use of the gain and the offset acquired by the gain/offset correction unit 8.

摘要翻译： 提供了一种电流控制半导体器件，其通过动态地校正增益a和偏移b的变化，以及使用该半导体器件的控制装置，能够以一个芯片的IC内的高精度检测电流。 晶体管4，电流 - 电压转换器电路22和AD转换器23设置在相同的半导体芯片上。 参考电流发生器电路6和6'将电流脉冲Ic叠加在负载2的电流上，并且改变由AD转换器输出的电压数字值。 增益/偏移校正单元8使由参考电流发生器电路6,6'引起的电压数字值的变化进行信号处理，并且以线性关系表达式动态地获取增益a，a'和偏移量b，b' 由AD转换器23输出的电压数字值和负载的当前数字值。 当前数字值计算单元12利用由增益/偏移校正单元8获取的增益和偏移来校正由AD转换器输出的电压值。

公开(公告)号：US09000966B2

公开(公告)日：2015-04-07

申请号：US14049994

申请日：2013-10-09

申请人： SK Hynix Inc.

发明人： Young-Chul Sohn

IPC分类号： H03M1/12 ,  H04N5/378 ,  H03M1/00

CPC分类号： H04N5/378 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/12 ,  H03M1/123 ,  H03M1/56

摘要： A integrated circuit includes an analog power domain circuit having more than one stages, a digital power domain circuit having at least one stage receiving the output signal of the analog power domain circuit, and a voltage regulating unit suitable for supplying at least one scaled power to the latter part of the stages to reduce a voltage level difference between the analog power domain circuit and the digital power domain circuit.

摘要翻译： 集成电路包括具有多于一个级的模拟功率域电路，具有至少一个级的数字功率域电路，其接收模拟功率域电路的输出信号，以及电压调节单元，适于将至少一个缩放的功率提供给 后期部分降低模拟功率域电路与数字电源电路之间的电压电平差。

公开(公告)号：US08994572B2

公开(公告)日：2015-03-31

申请号：US14346260

申请日：2012-09-06

申请人： Hao San ,  Tsubasa Maruyama ,  Masao Hotta

发明人： Hao San ,  Tsubasa Maruyama ,  Masao Hotta

IPC分类号： H03M1/34 ,  H03M1/14 ,  H03M1/06 ,  H03M1/12 ,  H03M1/40

CPC分类号： H03M1/14 ,  H03M1/0609 ,  H03M1/0692 ,  H03M1/0695 ,  H03M1/1014 ,  H03M1/1205 ,  H03M1/40 ,  H03M1/403 ,  H03M1/442

摘要： The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing. An A/D converter (1) of the invention, which is a cyclic type of analog/digital converter for converting an analog input signal to a digital signal having a predetermined resolution, comprises: a digital approximation unit (10) that includes a comparing unit (13) for comparing the magnitude of an input first analog signal with a threshold value to output a digital value indicating a result of the comparison and that also includes an MDAC unit (14) for amplifying the first analog signal to β-fold, where β is greater than one but smaller than two, and for executing a predetermined computation in accordance with the result of the comparison of the comparing unit to output a second analog signal; a multiplexer (20) that, if the MSB is to be computed, outputs the analog input signal and, otherwise, outputs the second analog signal as the first analog signal; a β estimating unit (30) that estimates the value of β; and a digital signal outputting unit (40) that sequentially takes in digital values outputted by the comparing unit and that outputs the taken-in digital values as the digital signal.

摘要翻译： 本发明的目的是提供一种A / D转换器，其由于制造变化而表现出较少的故障。 本发明的A / D转换器（1）是用于将模拟输入信号转换为具有预定分辨率的数字信号的循环型模拟/数字转换器，包括：数字近似单元（10），包括比较 单元（13），用于将输入的第一模拟信号的幅度与阈值进行比较，以输出指示比较结果的数字值，并且还包括用于将第一模拟信号放大到＆bgr;折叠的MDAC单元（14） ，其中＆bgr 大于1但小于2，并且用于根据比较单元的比较结果执行预定的计算以输出第二模拟信号; 多路复用器（20），如果要计算MSB，则输出模拟输入信号，否则输出第二模拟信号作为第一模拟信号; 一个 估计单位（30）估计值 以及数字信号输出单元（40），其顺序地取入由比较单元输出的数字值，并将所接收的数字值作为数字信号输出。

公开(公告)号：US08912934B2

公开(公告)日：2014-12-16

申请号：US13657214

申请日：2012-10-22

申请人： Marvell International Ltd.

发明人： George A. Zimmerman ,  William W. Jones

IPC分类号： H03M1/06 ,  H03M1/12

CPC分类号： H03M1/0609 ,  H03M1/0602 ,  H03M1/1215

摘要： A system includes converters, first modules, second modules, and a multiplexer. The converters receive an analog signal and a respective one of multiple clock signals. Each of the converters samples the analog signal based on a respective clock signal to generate a respective digital signal. Each of the clock signals is out-of-phase with other ones of the clock signals. The first modules receive the digital signals generated by the converters, remove bias offsets from the digital signals to generate first output signals, and output each of the first output signals on a multiple channels. The second modules receive the first output signals, and based on the first output signals, remove or equalize gain mismatch between the channels to generate second output signals. The multiplexer receives the second output signals, and generates an output based on the second output signals. The output is a digital representation of the analog signal.

摘要翻译： 系统包括转换器，第一模块，第二模块和多路复用器。 转换器接收模拟信号和多个时钟信号中的相应的一个。 每个转换器基于相应的时钟信号对模拟信号进行采样以产生相应的数字信号。 每个时钟信号与其他时钟信号不同相。 第一模块接收由转换器产生的数字信号，从数字信号中去除偏置偏移以产生第一输出信号，并且在多个通道上输出每个第一输出信号。 第二模块接收第一输出信号，并且基于第一输出信号，去除或均衡通道之间的增益失配以产生第二输出信号。 多路复用器接收第二输出信号，并且基于第二输出信号产生输出。 输出是模拟信号的数字表示。