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公开(公告)号：US11764798B2
公开(公告)日：2023-09-19
申请号：US17688942
申请日：2022-03-08
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Shih-Hsiung Huang
CPC classification number: H03M1/1019 , H03M1/123
Abstract: A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into a plurality of first digital codes, in which a first converter circuitry in the converter circuitries is configured to perform a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate control signals, and determines whether to set the second digital code to be a second corresponding digital code in predetermined digital codes according to the control signals.
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公开(公告)号：US11728818B2
公开(公告)日：2023-08-15
申请号：US17703396
申请日：2022-03-24
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Jung-Hsin Chu
CPC classification number: H03M1/1009 , H03M1/1019 , H03M1/1033 , H03M1/123
Abstract: A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into first digital codes. A first converter circuitry in the converter circuitries performs a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate first and second valid signals, and determines whether to set the second digital code to be a first predetermined digital code or a second predetermined digital code according to the first and the second valid signals. The second valid signal is a delay signal of the first valid signal.
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公开(公告)号：US20170244422A1
公开(公告)日：2017-08-24
申请号：US15590563
申请日：2017-05-09
Applicant: CANON KABUSHIKI KAISHA
Inventor： Seiji Hashimoto , Takeru Suzuki , Yasushi Matsuno , Takashi Muto
CPC classification number: H03M1/0609 , H03M1/1019 , H03M1/123 , H03M1/186 , H03M1/56 , H04N5/225 , H04N5/3355 , H04N5/378
Abstract: When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.
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4.发明授权公开(公告)号：US09503116B2
公开(公告)日：2016-11-22
申请号：US14955916
申请日：2015-12-01
Applicant: ANALOG DEVICES, INC.
Inventor： Carroll C. Speir , Eric Otte , Jeffrey Paul Bray
CPC classification number: H03M1/128 , H03M1/1019 , H03M1/1028 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/46 , H03M1/462 , H03M1/468 , H03M3/382 , H03M3/498
Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.
Abstract translation: 模数转换器（ADC）可能会产生可能影响其性能的错误。 为了提高性能，已经使用许多技术来补偿或纠正错误。 当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。 片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。 片上微处理器对于随机时间交织ADC特别有用。 此外，随机采样ADC可以并行添加到主ADC用于校准目的。 此外，整个系统可以包括用于校正ADC中的错误的有效实现。
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公开(公告)号：US20160182074A1
公开(公告)日：2016-06-23
申请号：US14955888
申请日：2015-12-01
Applicant: ANALOG DEVICES, INC.
Inventor： CARROLL C. SPEIR , ERIC OTTE , NEVENA RAKULJIC , JEFFREY PAUL BRAY
CPC classification number: H03M1/128 , H03M1/1019 , H03M1/1028 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/46 , H03M1/462 , H03M1/468 , H03M3/382 , H03M3/498
Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.
Abstract translation: 模数转换器（ADC）可能会产生可能影响其性能的错误。 为了提高性能，已经使用许多技术来补偿或纠正错误。 当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。 片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。 片上微处理器对于随机时间交织ADC特别有用。 此外，随机采样ADC可以并行添加到主ADC用于校准目的。 此外，整个系统可以包括用于校正ADC中的错误的有效实现。
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Patent Agency Ranking
6.发明授权公开(公告)号：US09337855B2
公开(公告)日：2016-05-10
申请号：US14532264
申请日：2014-11-04
Applicant: QUALCOMM Incorporated
Inventor： Ganesh Ramachandra Murthy Saripalli , Shahin Mehdizad Taleie , Michael Joseph McGowan , Jenny Kuo , Dongwon Seo , Jalal Ahmad Elhusseini
CPC classification number: H03M1/1009 , H03M1/1019 , H03M1/66 , H03M1/68 , H03M1/742
Abstract: A method and apparatus for a method of calibrating a transmit digital to analog converter full-scale current. The method comprises generating a tuned reference current and then calibrating the tuned reference current to a selected value in order to produce a predetermined current value. The calibration further comprises dividing a reference voltage input over a resistor string. A band gap current is then generated using the divided reference voltage input. A tuned current output is then produced from a current steering digital to analog converter with the tuned output current stored in a register. The reference current for the transmit DAC is then generated based on the stored tuned output current.
Abstract translation: 一种用于校准发射数模转换器满量程电流的方法和装置。 该方法包括产生调谐的参考电流，然后将调谐的参考电流校准到选定的值，以便产生预定的电流值。 该校准还包括对在电阻串上输入的参考电压进行分频。 然后使用划分的参考电压输入产生带隙电流。 然后，从调节输出电流存储在寄存器中的当前转向数字到模拟转换器产生调谐电流输出。 然后基于存储的调谐输出电流产生发射DAC的参考电流。
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公开(公告)号：US09244179B2
公开(公告)日：2016-01-26
申请号：US14360289
申请日：2012-12-04
Inventor： Frances W. Y. Lau , Craig Steven Levin , Mark A. Horowitz , Hwang Ho Choi , Jaeha Kim
IPC: G01T1/166 , G01T1/29 , G01T1/208 , H03M1/10 , H03F3/08 , H03M1/20 , E02D29/14 , G01T1/164 , G01T1/20 , G01T1/202 , A61B6/03 , A61B6/00
CPC classification number: G01T1/208 , A61B6/037 , A61B6/4208 , E02D29/1427 , G01T1/1647 , G01T1/2006 , G01T1/202 , G01T1/2985 , H03F3/08 , H03M1/1019 , H03M1/204
Abstract: An integrated circuit in a PET imaging system with a plurality of photo detectors is provided. A plurality of differential transimpedance amplifiers with differential inputs and differential outputs is provided, wherein differential inputs for each differential transimpedance amplifier of the plurality of differential transimpedance amplifiers are electrically connected to a photodetector. A plurality of level crossing analog-to-digital converters is provided wherein differential inputs for each level crossing analog-to-digital converter of the plurality of level crossing analog-to-digital converters are electrically connected to differential outputs of a differential transimpedance amplifier, wherein each level crossing analog-to-digital converter of the plurality of level crossing analog-to-digital converters, comprises a plurality of differential comparators with differential inputs and differential threshold inputs, wherein the differential inputs are electrically connected to the output of the differential outputs of the differential transimpedance amplifier electrically connected to the level crossing analog-to-digital converter and a clock.
Abstract translation: 提供了具有多个光电检测器的PET成像系统中的集成电路。 提供了具有差分输入和差分输出的多个差分跨阻放大器，其中多个差分跨阻抗放大器的每个差分跨阻放大器的差分输入电连接到光电检测器。 提供了多个电平交叉模数转换器，其中多个电平交叉模数转换器中的每个电平交叉模数转换器的差分输入电连接到差分跨阻放大器的差分输出， 其中所述多个电平交叉模数转换器中的每个电平交叉模拟 - 数字转换器包括具有差分输入和差分阈值输入的多个差分比较器，其中所述差分输入电连接到所述差分输出 电连接到电平交叉模数转换器的差分跨阻放大器的输出和时钟。
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8.发明授权公开(公告)号：US09214951B1
公开(公告)日：2015-12-15
申请号：US14291441
申请日：2014-05-30
Applicant: Realtek Semiconductor Corp.
Inventor： Chia-Liang (Leon) Lin
CPC classification number: H03M1/1019 , H03M1/10 , H03M1/1004 , H03M1/1009 , H03M1/1235 , H03M1/60
Abstract: A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal.
Abstract translation: 电路包括输入调度单元，用于接收输入信号和校准信号，并根据选择信号输出N个调度信号。 该电路还包括N个模拟 - 数字转换器（ADC）单元，用于分别接收N个调度信号，N个控制信号和N个映射表，并分别输出N个原始数据和N个精细数据。 输出调度单元接收N个精细数据并根据选择信号输出输出数据，校准控制器接收N个原始数据并输出选择信号，N个控制信号，N个映射表和数字代码 。 DAC（数模转换器）接收数字代码并输出校准信号，其中由选择信号指定的调度信号之一来自校准信号，而另一个调度信号来自输入信号。
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9.发明申请公开(公告)号：US20150349794A1
公开(公告)日：2015-12-03
申请号：US14291441
申请日：2014-05-30
Applicant: Realtek Semiconductor Corp.
Inventor： Chia-Liang (Leon) Lin
CPC classification number: H03M1/1019 , H03M1/10 , H03M1/1004 , H03M1/1009 , H03M1/1235 , H03M1/60
Abstract: A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal.
Abstract translation: 电路包括输入调度单元，用于接收输入信号和校准信号，并根据选择信号输出N个调度信号。 该电路还包括N个模拟 - 数字转换器（ADC）单元，用于分别接收N个调度信号，N个控制信号和N个映射表，并分别输出N个原始数据和N个精细数据。 输出调度单元接收N个精细数据并根据选择信号输出输出数据，校准控制器接收N个原始数据并输出选择信号，N个控制信号，N个映射表和数字代码 。 DAC（数模转换器）接收数字代码并输出校准信号，其中由选择信号指定的调度信号之一来自校准信号，而另一个调度信号来自输入信号。
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公开(公告)号：US09077357B2
公开(公告)日：2015-07-07
申请号：US14507265
申请日：2014-10-06
Applicant: Renesas Electronics Corporation
Inventor： Masumi Kon , Jou Kudou
CPC classification number: H03M1/36 , G01K15/007 , G01R27/02 , H03M1/0607 , H03M1/0617 , H03M1/1019 , H03M1/52
Abstract: To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage.
Abstract translation: 抑制测量电阻的检测精度由选择开关的导通电阻降低。 选择器开关设置在通过参考电阻耦合到第一电压的第一节点和通过测量电阻耦合到第二电压的多个第二节点之间，并且通过选择器开关选择要耦合到第一节点的第二节点。 校正电路产生通过将第二电压加到第二节点和第一节点之间的电压而获得的电压作为校正电压。 双积分ADC发现当校正电压与第一节点的电压的差分电压被积分到第一电压时经过第一积分时间，并且当第一电压与第一电压的电压 第一节点被集成到校正电压。
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