- 专利标题: Gain mismatch correction for voltage-to-delay preamplifier array
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申请号: US17133745申请日: 2020-12-24
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公开(公告)号: US11438001B2公开(公告)日: 2022-09-06
- 发明人: Narasimhan Rajagopal , Chirag Chandrahas Shetty , Neeraj Shrivastava , Prasanth K , Eeshan Miglani
- 申请人: Texas Instruments Incorporated
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Mark A. Valetti; Charles A. Brill; Frank D. Cimino
- 主分类号: H03M1/34
- IPC分类号: H03M1/34 ; H03M1/12 ; H03K5/24 ; H03L7/081 ; H03K5/00
摘要:
A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.
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