公开(公告)号：US09614510B2

公开(公告)日：2017-04-04

申请号：US15068231

申请日：2016-03-11

申请人： Texas Instruments Incorporated

发明人： Venkatesh Srinivasan ,  Kun Shi ,  Victoria Wang ,  Nikolaus Klemmer

IPC分类号： H03K5/159 ,  H03M3/00 ,  H03M1/16

CPC分类号： H03M3/38 ,  H03K5/159 ,  H03M1/001 ,  H03M1/164 ,  H03M3/37 ,  H03M3/386 ,  H03M3/464

摘要： System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

公开(公告)号：US09513651B2

公开(公告)日：2016-12-06

申请号：US14838918

申请日：2015-08-28

申请人： KAPIK INC.

发明人： Syed Imran Ahmed ,  James Andrew Cherry ,  William Martin Snelgrove

IPC分类号： H03M3/00 ,  G05F3/02 ,  H03M1/00 ,  H03M1/12

CPC分类号： G05F3/02 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/37 ,  H03M3/386 ,  H03M3/414 ,  H03M3/44 ,  H03M3/45 ,  H03M3/46

摘要： A system and method to achieve low power and/or low supply operation of a delta-sigma modulator by taking advantage of the inherent virtual ground of the delta-sigma loop to make the input to a low power integrator small and largely independent of the input signal. This results in improved linearity of the integrator and relaxed constraints on the supply for the first stage integrator. The architecture also enables direct access to the quantization error of the feedback loop and thus can be used to either/or: 1. Calibrate the modulator, 2. Achieve reduced quantization noise, 3. Stabilize the loop by compensating for excess loop delay. Low voltage common-mode-feedback is also achieved using the techniques described.

摘要翻译： 通过利用Δ-Σ回路的固有虚拟接地来实现Δ-Σ调制器的低功率和/或低电源工作以使低功率积分器的输入小而且很大程度上独立于输入的系统和方法 信号。 这导致积分器的线性度提高，并且对第一级积分器的供给放宽了约束。 该架构还可以直接访问反馈回路的量化误差，因此可以用于/或：1.校准调制器，2.实现降低的量化噪声，3.通过补偿多余的环路延迟来稳定环路。 使用所述技术也可实现低压共模反馈。

公开(公告)号：US20160072520A1

公开(公告)日：2016-03-10

申请号：US14944182

申请日：2015-11-17

申请人： Syntropy Systems, LLC

发明人： Christopher Pagnanelli

IPC分类号： H03M3/00 ,  G06F17/10

CPC分类号： H03M3/404 ,  G06F17/10 ,  H03M3/358 ,  H03M3/386 ,  H03M3/422 ,  H03M3/436 ,  H03M3/468 ,  H03M3/498

摘要： Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. Each of the processing branches includes a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit coupled to an output of the continuous-time quantization-noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the digital-to-analog converter circuit back into the continuous-time quantization-noise-shaping circuit. A center frequency of the digital bandpass filter in each the processing branch corresponds to a minimum in a quantization noise transfer function for the continuous-time quantization-noise-shaping circuit in the same processing branch.

公开(公告)号：US20110309959A1

公开(公告)日：2011-12-22

申请号：US13127039

申请日：2009-10-29

申请人： Jean-Michel Hode ,  Leila Kamoun

发明人： Jean-Michel Hode ,  Leila Kamoun

IPC分类号： H03M1/20 ,  H03M1/12

CPC分类号： H03M3/386 ,  H03M3/344 ,  H03M3/402 ,  H03M3/414

摘要： In a method for improving resolution and for correcting distortions for a sigma-delta modulator, a modulator converts an analog input signal into a secondary output digital signal sampled at a frequency fe and coded on NB bits, a second main output digital signal s′(t) is represented on NMSB bits also being available at the output. At least three processings are applied successively to the outputs, a first processing carrying out a demodulation by a frequency f0 and a decimation of factor N in an independent manner, z second processing carrying out an improvement of the resolution and a third processing carrying out a correction of the distortions. These three processings are carried out after decimation. A sigma-delta modulator implements the method.

摘要翻译： 在用于提高分辨率和用于校正Σ-Δ调制器的失真的方法中，调制器将模拟输入信号转换为以频率fe采样并以NB位编码的次输出数字信号，第二主输出数字信号s'（ t）在输出端也可用的NMSB位表示。 对输出连续施加至少三个处理，以独立方式执行频率f0的解调和因子N的抽取的第一处理，执行分辨率提高的第二处理和执行分辨率的第三处理 纠正扭曲。 这三个处理在抽取后进行。 Σ-Δ调制器实现该方法。

公开(公告)号：US07944385B2

公开(公告)日：2011-05-17

申请号：US12161532

申请日：2007-01-22

申请人： Yann Le Guillou

发明人： Yann Le Guillou

IPC分类号： H03M3/00

CPC分类号： H03M3/386 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

摘要： A continuous-time sigma-delta analog-to-digital converter (CV) including i) a signal path (SP) having at least one combiner (C1) for combining analog signals to convert with feedback analog signals, at least two integrators (H1, H5), mounted in series, to integrate the combined analog signals, a quantizer (Q) for converting the integrated signals into digital signals, and a decimation filter (DF) for filtering digital signals, and ii) a feedback path (FP) having at least a digital-to-analog converter (DAC) for converting the digital signals output by the quantizer (Q) into feedback analog signals intended for the combiner (C1). Each integrator (H1, H5) having variable capacitance means arranged to be set in chosen states defined by the values of a digital word, to present the chosen capacitances.

摘要翻译： 一种连续时间Σ-Δ模数转换器（CV），包括i）具有至少一个用于组合模拟信号以与反馈模拟信号一起转换的组合器（C1）的信号路径（SP），至少两个积分器 ，H5），用于集成组合的模拟信号，用于将积分信号转换为数字信号的量化器（Q）和用于对数字信号进行滤波的抽取滤波器（DF），以及ii）反馈路径（FP） 具有用于将由量化器（Q）输出的数字信号转换成用于组合器（C1）的反馈模拟信号的至少一个数模转换器（DAC）。 具有可变电容装置的每个积分器（H1，H5）被布置成被设置在由数字字的值定义的选定状态中，以呈现所选择的电容。

公开(公告)号：US07796072B2

公开(公告)日：2010-09-14

申请号：US12255038

申请日：2008-10-21

申请人： Antonio Di Giandomenico ,  David San Segundo Bello ,  Andreas Wiesbauer ,  Fabio Ballarin ,  Martin Clara

发明人： Antonio Di Giandomenico ,  David San Segundo Bello ,  Andreas Wiesbauer ,  Fabio Ballarin ,  Martin Clara

IPC分类号： H03M3/00

CPC分类号： H03M3/386 ,  H03M3/458

摘要： Modulation circuits for operating in at least a first and second mode are described herein.

摘要翻译： 至少在第一和第二模式下操作的调制电路在此描述。

公开(公告)号：US07688236B2

公开(公告)日：2010-03-30

申请号：US11865539

申请日：2007-10-01

申请人： Antonio Di Giandomenico ,  Martin Clara ,  David San Segundo Bello ,  Wolfgang Klatzer ,  Luca Gori ,  Andreas Wiesbauer

发明人： Antonio Di Giandomenico ,  Martin Clara ,  David San Segundo Bello ,  Wolfgang Klatzer ,  Luca Gori ,  Andreas Wiesbauer

IPC分类号： H03M1/10

CPC分类号： H03M1/1033 ,  H03M1/742 ,  H03M3/386 ,  H03M3/424 ,  H03M3/454

摘要： In an integrated circuit including a first multibit digital-to-analog converter and a second multibit digital-to-analog converter, a calibration circuit is provided which is shared between the first and second digital-to-analog converters.

摘要翻译： 在包括第一多位数模转换器和第二多位数模转换器的集成电路中，提供了在第一和第二数模转换器之间共享的校准电路。

公开(公告)号：US07095345B2

公开(公告)日：2006-08-22

申请号：US10936179

申请日：2004-09-08

申请人： Khiem Nguyen ,  Robert W. Adams

发明人： Khiem Nguyen ,  Robert W. Adams

IPC分类号： H03M1/10

CPC分类号： H03M3/386 ,  H03J1/0091 ,  H03J2200/10 ,  H03M3/458

摘要： A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

摘要翻译： 使用混合调谐电路，包括数字有限状态机和模拟调谐电路，以有效地保持连续时间积分器的RC乘积在过程，温度，电源和采样率变化之间恒定。 由于实施是连续的，跟踪比传统技术更准确。 使用精心挑选的时钟方案，该技术消除了反馈DAC中的符号间干扰。 该技术不使用参考频率，从而消除了用户识别参考频率的需要。

公开(公告)号：US11909420B2

公开(公告)日：2024-02-20

申请号：US17808165

申请日：2022-06-22

申请人： ANRITSU CORPORATION

发明人： Ittetsu Kaji ,  Kayoko Horiuchi

IPC分类号： H03M1/00 ,  H03M3/00 ,  G01R35/00 ,  G01R31/319

CPC分类号： H03M3/502 ,  H03M3/386 ,  G01R31/319 ,  G01R35/00

摘要： There are provided a signal generation unit that generates a predetermined digital signal, a level conversion unit that converts a level of the digital signal generated by the signal generation unit, a DA converter that converts the digital signal of which the level is converted by the level conversion unit into an analog signal in a predetermined intermediate frequency bandwidth, and a control unit that creates correction data for correcting a linearity of a level of an output signal of the DA converter for all frequencies to be used, based on actual data which is data of a level of an actual output signal when a setting of the level of the output signal of the DA converter is changed at a predetermined level interval, at a predetermined frequency, and converts a level of an input signal of the DA converter with the correction data.

公开(公告)号：US10084473B2

公开(公告)日：2018-09-25

申请号：US15455971

申请日：2017-03-10

申请人： Texas Instruments Incorporated

发明人： Venkatesh Srinivasan ,  Kun Shi ,  Victoria Wang ,  Nikolaus Klemmer

IPC分类号： H03M3/00 ,  H03M1/00 ,  H03K5/159

CPC分类号： H03M3/38 ,  H03K5/159 ,  H03M1/001 ,  H03M1/164 ,  H03M3/37 ,  H03M3/386 ,  H03M3/464

摘要： System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.