公开(公告)号：US09628104B2

公开(公告)日：2017-04-18

申请号：US14657323

申请日：2015-03-13

申请人： Rosemount Inc.

发明人： Rongtai Wang ,  John Paul Schulte

IPC分类号： G01L9/12 ,  H03M3/00 ,  G01D5/24

CPC分类号： H03M3/39 ,  G01D5/24 ,  G01L9/0072 ,  G01L9/0075 ,  G01L9/12 ,  H03M3/356 ,  H03M3/376 ,  H03M3/494

摘要： A single plate capacitance sensor includes a sensor capacitor and a reference capacitor that share common plate. A capacitance-to-digital sigma delta modulator provides separate sensor excitation and reference excitation signals to the sensor capacitor and the reference capacitor to provide high resolution detection. Programmable ratio-metric excitation voltages and adaptive excitation voltage sources can be used to enhance modulator performance.

公开(公告)号：US20110254718A1

公开(公告)日：2011-10-20

申请号：US13166518

申请日：2011-06-22

申请人： Kazuo MATSUKAWA ,  Shiro DOSHO ,  Yosuke MITANI ,  Koji OBATA

发明人： Kazuo MATSUKAWA ,  Shiro DOSHO ,  Yosuke MITANI ,  Koji OBATA

IPC分类号： H03M3/00 ,  G06G7/18

CPC分类号： H03M3/376 ,  H03M3/43 ,  H03M3/454

摘要： An integrator is provided which can reduce a disturbance in the current waveform of a current DA converter in order to improve the SNR of a ΔΣ modulator, for example. The integrator includes an operational amplifier, and feedback paths provided in parallel between the output terminal and inverting input terminal of the operational amplifier. In one of the feedback paths, an integrating capacitor and at least one resistor are connected in series. In the other feedback path, a second integrating capacitor whose capacitance value is smaller than that of the integrating capacitor is provided.

摘要翻译： 提供了一种积分器，其可以减小当前DA转换器的电流波形中的干扰，以便提高＆Dgr＆amp; 调制器。 积分器包括运算放大器，并且在运算放大器的输出端和反相输入端之间并联提供反馈路径。 在其中一个反馈路径中，积分电容器和至少一个电阻器串联连接。 在另一个反馈路径中，提供了电容值小于积分电容器的第二积分电容器。

公开(公告)号：US07671776B1

公开(公告)日：2010-03-02

申请号：US12141100

申请日：2008-06-18

申请人： Giri Rangan ,  Bhupendra Sharma

发明人： Giri Rangan ,  Bhupendra Sharma

IPC分类号： H03M1/66

CPC分类号： H03M3/376 ,  H03M3/43 ,  H03M3/452

摘要： Circuits, methods, and apparatus that provide sampling networks that avoid undesired transient voltages. One example provides a sampling network that includes a switch such that charge is transferred to an integrator in two separate steps instead of one. This switch connects the first side of a capacitor to an intermediate voltage after it is connected to an input voltage and before it is connected to a reference voltage, where the reference voltage is the output of a one-bit digital-to-analog converter. This intermediate switching allows charge to be transferred from a sampling capacitor to an integrating capacitor in two steps, thus avoiding undesirable transient voltages.

摘要翻译： 提供避免不必要的瞬态电压的采样网络的电路，方法和设备。 一个示例提供了包括开关的采样网络，使得电荷以两个单独的步骤而不是一个转移到积分器。 该开关在连接到输入电压并且在连接到参考电压之前将电容器的第一侧连接到中间电压，其中参考电压是1位数模转换器的输出。 该中间开关允许电荷从采样电容器分两步传递到积分电容器，从而避免不期望的瞬态电压。

公开(公告)号：US20090027247A1

公开(公告)日：2009-01-29

申请号：US12178244

申请日：2008-07-23

申请人： Toshio KUMAMOTO ,  Takashi Okuda

发明人： Toshio KUMAMOTO ,  Takashi Okuda

IPC分类号： H03M3/02 ,  H03M3/00

CPC分类号： H03M3/376 ,  H03M3/452

摘要： In an A/D converter including a switched capacitor integration circuit, to suppress an effect of a noise generated in the switched capacitor circuit while suppressing increase in a forming area of the circuit. A first-stage integrator of a differential input type A/D converter includes first and second switched capacitor circuits, and includes a noise cancel circuit for generating a noise cancel signal to cancel a kickback noise generated due to switching operation thereof.

摘要翻译： 在包括开关电容器积分电路的A / D转换器中，抑制在开关电容器电路中产生的噪声的影响，同时抑制电路的形成区域的增加。 差分输入型A / D转换器的第一级积分器包括第一和第二开关电容器电路，并且包括用于产生噪声消除信号的噪声消除电路，以消除由于其切换操作而产生的反冲噪声。

公开(公告)号：US07345608B2

公开(公告)日：2008-03-18

申请号：US11609477

申请日：2006-12-12

申请人： Wei-Hsuan Tu ,  Tse-Hsiang Hsu

发明人： Wei-Hsuan Tu ,  Tse-Hsiang Hsu

IPC分类号： H03M3/00

CPC分类号： H03M3/346 ,  H03M3/376 ,  H03M3/502 ,  H03M3/504

摘要： A Delta-Sigma DAC is provided, comprising an interpolator, a Delta-Sigma modulator, a FIR filter and an analog filter. The interpolator oversamples a n-bit digital signal to generate a n-bit oversampled signal. The Delta-Sigma modulator coupled to the output of interpolator shapes the n-bit oversampled digital signal to generate a shaped digital signal. The FIR filter coupled to the Delta-Sigma modulator filters the shaped digital signal to generate an analog audio signal. The analog filter coupled to the FIR filter amplifies the analog audio signal to generate a audible signal.

摘要翻译： 提供了一种Delta-Sigma DAC，包括内插器，Δ-Σ调制器，FIR滤波器和模拟滤波器。 内插器过采样n位数字信号以产生n位过采样信号。 耦合到内插器的输出的Δ-Σ调制器对n位过采样的数字信号进行整形，以产生成形的数字信号。 耦合到Δ-Σ调制器的FIR滤波器对形状的数字信号进行滤波以产生模拟音频信号。 耦合到FIR滤波器的模拟滤波器放大模拟音频信号以产生可听信号。

公开(公告)号：US5974089A

公开(公告)日：1999-10-26

申请号：US898544

申请日：1997-07-22

申请人： Adya S. Tripathi ,  Cary L. Delano

发明人： Adya S. Tripathi ,  Cary L. Delano

IPC分类号： H03M3/02 ,  H04B14/06

CPC分类号： H04B14/06 ,  H03M3/376 ,  H03M3/43 ,  H03M3/454

摘要： The transition time of power switching devices ultimately limits the rate at which such devices can be switched. Because the occurrence of unacceptably narrow pulses is relatively rare in an oversampled, noise-shaping signal processor, the elimination of such narrow pulses is introduced through the use of circuitry in the modulator loop which constrains the time between transitions to be greater than or equal to some minimum time period which, in turn provides for a smooth interface to power switching devices. However, because of the delay introduced by this pulse qualification circuitry, the modulator loop sampling frequency is increased to deal with any resulting instability. Thus, an oversampled, noise shaping signal processor is described having at least one integrator stage in a feedback loop. A sampling stage in the feedback loop is coupled to the at least one integrator stage. The sampling stage samples an analog signal at a sample frequency. Qualification logic coupled to the sampling stage receives a pulse waveform therefrom, and ensures that signal transitions in the pulse waveform occur more than a first time period apart and that the waveform can therefore be handled by, for example, a power switching device. A switching stage in the feedback loop is coupled to the qualification logic. The signal processor has a feedback path from the output of the switching stage to the input of the at least one integrator stage thereby closing the feedback loop.

摘要翻译： 功率开关器件的转换时间最终限制了这种器件可以切换的速率。 因为在过采样的噪声整形信号处理器中出现不可接受的窄脉冲是相对较少的，所以通过使用调制器环路中的电路来引入这种窄脉冲的消除，这将限制转换之间的时间大于或等于 一些最小时间段，这反过来又提供了一个平滑的接口给电源开关设备。 然而，由于由该脉冲鉴定电路引入的延迟，调制器环路采样频率被增加以处理任何导致的不稳定性。 因此，描述过采样的噪声整形信号处理器在反馈回路中具有至少一个积分器级。 反馈回路中的采样级耦合到至少一个积分器级。 采样级以采样频率采样模拟信号。 耦合到采样级的限定逻辑从其接收脉冲波形，并且确保脉冲波形中的信号转换比第一时间间隔多出，并且波形因此可以由例如功率开关器件来处理。 反馈回路中的开关级耦合到限定逻辑。 信号处理器具有从开关级的输出到至少一个积分器级的输入的反馈路径，从而闭合反馈回路。

公开(公告)号：US11881874B2

公开(公告)日：2024-01-23

申请号：US17674788

申请日：2022-02-17

申请人： INVENSENSE, INC.

发明人： Gabriele Pelli

IPC分类号： H03M3/00 ,  H03F3/45 ,  G01C19/5712 ,  G01P1/00 ,  G01P15/08 ,  G01C19/5776 ,  G01C19/5649

CPC分类号： H03M3/376 ,  G01C19/5649 ,  G01C19/5712 ,  G01C19/5776 ,  G01P1/00 ,  G01P15/08 ,  H03F3/45 ,  H03M3/34 ,  H03M3/458 ,  H03M3/464 ,  H03F2203/45151 ,  H03F2203/45546

摘要： A motion sensor with sigma-delta analog-to-digital converter (ADC) having improved bias instability is presented herein. Differential outputs of a differential amplifier of the sigma-delta ADC are electrically coupled, via respective capacitances, to differential inputs of the differential amplifier. To minimize bias instability corresponding to flicker noise that has been injected into the differential inputs, the differential inputs are electrically coupled, via respective pairs of electronic switches, to feedback resistances based on a pair of switch control signals. In this regard, a first feedback resistance of the feedback resistances is electrically coupled to a first defined voltage, and a second feedback resistance of the feedback resistances is electrically coupled to a second defined reference voltage. The differential outputs are electrically coupled to differential inputs of a differential comparator of the sigma-delta ADC, and complementary outputs of the differential comparator comprise the pair of switch control signals.

公开(公告)号：US20160265995A1

公开(公告)日：2016-09-15

申请号：US14657323

申请日：2015-03-13

申请人： Rosemount Inc.

发明人： Rongtai Wang ,  John Paul Schulte

IPC分类号： G01L9/00 ,  H03M3/00

CPC分类号： H03M3/39 ,  G01D5/24 ,  G01L9/0072 ,  G01L9/0075 ,  G01L9/12 ,  H03M3/356 ,  H03M3/376 ,  H03M3/494

摘要： A single plate capacitance sensor includes a sensor capacitor and a reference capacitor that share common plate. A capacitance-to-digital sigma delta modulator provides separate sensor excitation and reference excitation signals to the sensor capacitor and the reference capacitor to provide high resolution detection. Programmable ratio-metric excitation voltages and adaptive excitation voltage sources can be used to enhance modulator performance.

摘要翻译： 单板电容传感器包括传感器电容器和共用共用板的参考电容器。 电容数字Σ-Δ调制器向传感器电容器和参考电容器提供单独的传感器激励和参考激励信号，以提供高分辨率检测。 可编程比率公制激励电压和自适应激励电压源可用于增强调制器性能。

公开(公告)号：US08878710B2

公开(公告)日：2014-11-04

申请号：US13677674

申请日：2012-11-15

申请人： STMicroelectronics International N.V.

发明人： Ankur Bal ,  Neha Bhargava ,  Anupam Jain

IPC分类号： H03M3/00 ,  H03M1/12

CPC分类号： H03M3/30 ,  H03M3/344 ,  H03M3/376 ,  H03M3/462

摘要： In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

摘要翻译： 在一个实施例中，对一组输入样本进行滤波，以使用N抽头滤波器提供一组滤波样本。 N抽头滤波器的稳态响应输出样本由滤波样本集合的第N / 2个样本确定。

公开(公告)号：US07786916B2

公开(公告)日：2010-08-31

申请号：US12203542

申请日：2008-09-03

申请人： Simon Kenneth Quinn ,  Andrew James Howlett

发明人： Simon Kenneth Quinn ,  Andrew James Howlett

IPC分类号： H03M1/66

CPC分类号： H03M1/0614 ,  H03M1/0872 ,  H03M1/804 ,  H03M3/358 ,  H03M3/376 ,  H03M3/502

摘要： A multi-bit digital to analog converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analog output signal (Vout+/Vout−). An array of further capacitors (C0-CN) correspond in number at least to the number of data bits (D0-DN) to be converted. The capacitors (Cf, C0-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P2) in which the further capacitors are connected (S3, S4) to reference voltages selected in accordance with the values of the data bits, (ii) an equalization phase (P6a) in which the further capacitors are connected (S2) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P6b) in which the parallel connected further capacitors are connected (S1, S5) in parallel with the first capacitor. The equalization phase masks nonlinearities arising in switches (S2) and thereby improves harmonic distortion.

摘要翻译： 多位数模转换器由开关电容器布置来实现，其中存储电容器（Cf）累积表示期望的模拟输出信号（Vout + / Vout-）的电荷。 另外的电容器（C0-CN）的数组至少与要转换的数据位数（D0-DN）相对应。 电容器（Cf，C0-CN）选择性地互相互连，并且以参考电压源（Vmid，Vdd，Vss）以相对重复的序列相包括（i）其中电容器连接的采样相位（P2） （S3，S4）根据数据位的值选择的参考电压，（ii）彼此并联连接另外的电容器（S2）的均衡相位（P6a），而不将它们与 第一电容器，之后是（iii）与第一电容器并联连接并联的另外的电容器（S1，S5）的转移相位（P6b）。 均衡相屏蔽了开关（S2）中出现的非线性，从而改善了谐波失真。