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公开(公告)号：US07671776B1
公开(公告)日：2010-03-02
申请号：US12141100
申请日：2008-06-18
申请人： Giri Rangan , Bhupendra Sharma
发明人： Giri Rangan , Bhupendra Sharma
IPC分类号： H03M1/66
摘要： Circuits, methods, and apparatus that provide sampling networks that avoid undesired transient voltages. One example provides a sampling network that includes a switch such that charge is transferred to an integrator in two separate steps instead of one. This switch connects the first side of a capacitor to an intermediate voltage after it is connected to an input voltage and before it is connected to a reference voltage, where the reference voltage is the output of a one-bit digital-to-analog converter. This intermediate switching allows charge to be transferred from a sampling capacitor to an integrating capacitor in two steps, thus avoiding undesirable transient voltages.
摘要翻译： 提供避免不必要的瞬态电压的采样网络的电路，方法和设备。 一个示例提供了包括开关的采样网络，使得电荷以两个单独的步骤而不是一个转移到积分器。 该开关在连接到输入电压并且在连接到参考电压之前将电容器的第一侧连接到中间电压，其中参考电压是1位数模转换器的输出。 该中间开关允许电荷从采样电容器分两步传递到积分电容器，从而避免不期望的瞬态电压。
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公开(公告)号：US07710164B1
公开(公告)日：2010-05-04
申请号：US12141099
申请日：2008-06-18
申请人： Bhupendra Sharma
发明人： Bhupendra Sharma
IPC分类号： G11C27/02
CPC分类号： G11C5/145 , G11C27/02 , H03K17/063
摘要： Circuits, methods, and apparatus that provide bootstrapped switches having improved reliability. One example improves the reliability of a discharge transistor connected to discharge the gate of a switch transistor by decreasing its operating voltage during the discharge. This example provides a discharge transistor having a first source-drain region connected to a gate of a switch transistor. Since the gate of the switch transistor can reach high voltages, if the discharge transistor's second source-drain region is instantaneously tied to ground when the switch's gate is discharged, the discharge transistor's reliability can be degraded due to hot-electron effects. Accordingly, instead of being connected to ground—or an intermediate node that quickly reaches the ground potential during gate discharge—the second source-drain region of the discharge transistor is coupled to an intermediate node that discharges to ground at a slower rate.
摘要翻译： 提供自举交换机的电路，方法和设备具有改进的可靠性。 一个例子通过在放电期间降低其工作电压来提高连接到放电开关晶体管的栅极的放电晶体管的可靠性。 该示例提供了具有连接到开关晶体管的栅极的第一源极 - 漏极区域的放电晶体管。 由于开关晶体管的栅极可以达到高电压，所以如果放电晶体管的第二源极 - 漏极区域在开关栅极放电时瞬间接地，则由于热电子效应，放电晶体管的可靠性会降低。 因此，放电晶体管的第二源极 - 漏极区域不是连接到接地或在栅极放电期间快速达到接地电位的中间节点，而是以较慢的速率耦合到放电到地的中间节点。
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3.发明授权Avoiding excessive cross-terminal voltages of low voltage transistors due to undesirable supply-sequencing in environments with higher supply voltages 有权在较高电源电压的环境中，由于不合需要的电源顺序，避免了过低的低压晶体管电压公开(公告)号：US07176749B2
公开(公告)日：2007-02-13
申请号：US10711532
申请日：2004-09-24
CPC分类号： G05F3/205
摘要： Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient bias current may be ensured by generating a primary bias current from a low supply voltage and a backup bias current from a high supply voltage, and providing the backup bias current as the bias current if the primary bias current is not present. The primary bias current may be provided as the bias current when the low supply voltage is available. Thus, the backup bias current is provided as bias current in case of undesirable supply sequencing.
摘要翻译： 确保足够的偏置电流被提供给包含以高电源电压工作的低压晶体管的电路的一部分。 可以通过从低电源电压和来自高电源电压的备用偏置电流产生初级偏置电流来确保这种足够的偏置电流，并且如果不存在初级偏置电流，则提供备用偏置电流作为偏置电流。 当低电源电压可用时，初级偏置电流可以作为偏置电流提供。 因此，在不期望的电源顺序的情况下，备用偏置电流被提供为偏置电流。
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公开(公告)号：US07034611B2
公开(公告)日：2006-04-25
申请号：US10855464
申请日：2004-05-27
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/086 , H03F3/3064 , H03F3/45659
摘要： A technique to attenuate even-order harmonics of an output stage of a multistage nested Miller compensation circuit. In one example embodiment, this is accomplished by using a low-bandwidth low-swing amplifier in the common mode feedback loop to improve the even-order harmonic performance in the signal path. The technique uses a separate multistage loop for the common mode feedback loop to attenuate the even-order harmonics. The common mode feedback loop is the fourth stage and uses the third stage of the nested Miller compensation circuit. The fourth stage of the common mode feedback loop includes a single harmonic and uses a low voltage supply to achieve lower power consumption by the common mode feedback loop.
摘要翻译： 一种衰减多级嵌套米勒补偿电路输出级偶次谐波的技术。 在一个示例实施例中，这是通过在共模反馈环路中使用低带宽低摆幅放大器来实现的，以改善信号路径中的偶次谐波性能。 该技术使用单独的多级环路来进行共模反馈环路，以衰减偶次谐波。 共模反馈回路是第四阶段，并使用嵌套的米勒补偿电路的第三级。 共模反馈回路的第四阶段包括单次谐波，并使用低压电源来实现共模反馈回路的较低功耗。
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公开(公告)号：US20050174171A1
公开(公告)日：2005-08-11
申请号：US10855464
申请日：2004-05-27
CPC分类号： H03F3/45183 , H03F1/086 , H03F3/3064 , H03F3/45659
摘要： A technique to attenuate even-order harmonics of an output stage of a multistage nested Miller compensation circuit. In one example embodiment, this is accomplished by using a low-bandwidth low-swing amplifier in the common mode feedback loop to improve the even-order harmonic performance in the signal path. The technique uses a separate multistage loop for the common mode feedback loop to attenuate the even-order harmonics. The common mode feedback loop is the fourth stage and uses the third stage of the nested Miller compensation circuit. The fourth stage of the common mode feedback loop includes a single harmonic and uses a low voltage supply to achieve lower power consumption by the common mode feedback loop.
摘要翻译： 一种衰减多级嵌套米勒补偿电路输出级偶次谐波的技术。 在一个示例实施例中，这是通过在共模反馈环路中使用低带宽低摆幅放大器来实现的，以改善信号路径中的偶次谐波性能。 该技术使用单独的多级环路来进行共模反馈环路，以衰减偶次谐波。 共模反馈回路是第四阶段，并使用嵌套的米勒补偿电路的第三级。 共模反馈回路的第四阶段包括单次谐波，并使用低压电源来实现共模反馈回路的较低功耗。
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