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公开(公告)号：US08830104B2
公开(公告)日：2014-09-09
申请号：US13187975
申请日：2011-07-21
IPC分类号： H03M1/12
摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).
摘要翻译： 公开了电路和系统的示例性实施方式，以及用于信号处理的方法，包括通过无源脉冲调制模数转换器（PMADC）实现的振幅和频带限制信号的采样和量化。
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公开(公告)号：US20110279296A1
公开(公告)日：2011-11-17
申请号：US13187975
申请日：2011-07-21
IPC分类号： H03M1/12
摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).
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公开(公告)号：US20110109489A1
公开(公告)日：2011-05-12
申请号：US12615994
申请日：2009-11-10
摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).
摘要翻译： 公开了电路和系统的示例性实现方式，以及用于信号处理的方法，包括通过无源脉冲调制模数转换器（PMADC）实现的振幅和频带限制信号的采样和量化。
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公开(公告)号：US08018366B2
公开(公告)日：2011-09-13
申请号：US12615994
申请日：2009-11-10
IPC分类号： H03M1/12
摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).
摘要翻译： 公开了电路和系统的示例性实施方式，以及用于信号处理的方法，包括通过无源脉冲调制模数转换器（PMADC）实现的振幅和频带限制信号的采样和量化。
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公开(公告)号：US20170288529A1
公开(公告)日：2017-10-05
申请号：US15083915
申请日：2016-03-29
申请人： Holger Wenske , Stephan Henzler
发明人： Holger Wenske , Stephan Henzler
摘要： Some embodiments include apparatus and methods for using a direct-current to direct-current (DCDC) converter and a control unit coupled to the DCDC converter. The DCDC converter includes a first node to receive an input signal, a second node to couple to a terminal of an inductor, and a third node to couple to an output node. The DCDC converter includes a driver controlled by a signal. The control unit is arranged to generate control information based on a duty cycle of the signal to control the duty cycle range of the signal.
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公开(公告)号：US20140137656A1
公开(公告)日：2014-05-22
申请号：US14233809
申请日：2012-06-01
IPC分类号： G01D11/24
CPC分类号： G01D11/245 , G01D11/30 , G01L19/143
摘要： The invention relates to a sensor device (10), in particular for use in a motor vehicle, having a housing (11) for accommodating a sensor element (1), wherein the sensor element (1) has electrical contact areas (2, 3) which are connected to electrical plug connections (18, 19) arranged in the housing (11) in an electrically conductive manner in the region of contacts (23, 24) of the plug connections (18, 19), wherein a force is applied to the sensor element (1) for the purpose of making electrical contact with a housing element in the direction of the plug connections (18, 19). The invention provides for the electrical plug connections (18, 19) to be arranged in a stationary manner in the housing (11) in the region of the contacts (23, 24) with the electrical contact areas (2, 3) of the sensor element (1), and for a support to be formed between the sensor element (1) and the housing (11) in such a manner that the sensor element (1) has three-point contact in the housing (11).
摘要翻译： 本发明涉及一种特别用于机动车辆的传感器装置（10），其具有用于容纳传感器元件（1）的壳体（11），其中传感器元件（1）具有电接触区域（2,3） ），其连接到在插头连接件（18,19）的触头（23,24）的区域中以导电方式布置在壳体（11）中的电插头连接（18,19），其中施加力 到传感器元件（1），以便在插头连接（18,19）的方向上与壳体元件电接触。 本发明提供了在触头（23,24）的区域中以固定方式布置在壳体（11）中的电插头连接（18,19），其中传感器的电接触区域（2,3） 元件（1），以及用于在传感器元件（1）和壳体（11）之间形成的支撑件，使得传感器元件（1）在壳体（11）中具有三点接触。
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公开(公告)号：US20110169673A1
公开(公告)日：2011-07-14
申请号：US12684771
申请日：2010-01-08
申请人： Stephan Henzler
发明人： Stephan Henzler
IPC分类号： H03M1/00
CPC分类号： G04F10/005 , H03M1/10
摘要： Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices.
摘要翻译： 这里描述与时间 - 数字转换器（TDC）相关的装置和方法。 通常，时间 - 数字转换器是测量时间段或时间间隔并输出表示测量时间段的数字值的装置。 在实现中，提供了一种包括时间 - 数字转换器电路的装置，其还包括内置自检（BIST）。 可以使用经由一个或多个多路复用器装置耦合到时间 - 数字转换器的一个或多个振荡器来实现内置自检。
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8.发明授权公开(公告)号：US07958418B2
公开(公告)日：2011-06-07
申请号：US12028657
申请日：2008-02-08
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.
摘要翻译： 电路装置可以包括具有用于接收测试信号的测试输入的扫描测试输入级，其中扫描测试输入级可以以高阻抗状态切换; 数据输入级具有用于接收数据信号的数据输入，其中数据输入级可以以高阻抗状态切换。 电路装置还可以包括耦合到扫描测试输入级的至少一个输出端和数据输入级的至少一个输出端的锁存器; 以及驱动电路，其被配置为产生用于数据输入级的脉冲时钟信号和用于驱动扫描测试输入级的信号。
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公开(公告)号：US07656204B2
公开(公告)日：2010-02-02
申请号：US11713544
申请日：2007-03-02
申请人： Stephan Henzler , Siegmar Koeppe
发明人： Stephan Henzler , Siegmar Koeppe
CPC分类号： H03K3/356191 , H03K3/012 , H03K5/00006 , H03K5/15013 , H03K2005/00286
摘要： A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input. The internal storage nodes of the buffer store elements are either pre-charged at the pre-charge potential or store a logic level, depending on the relevant input clock signals. The differential data inputs of one of the buffer store elements is connected to the internal storage nodes of the other buffer store element and pulsed signals can be tapped off at the internal differential storage node.
摘要翻译： 分频器电路包括至少两个时钟沿控制的差分缓冲器存储器元件，每个元件由互补的输入时钟信号计时，每个时钟信号包括可预充电到预充电电位的内部存储节点，并且每个包括差分数据输入。 缓冲存储器元件的内部存储节点或者是以预充电电位预充电，或根据相关的输入时钟信号存储逻辑电平。 缓冲存储元件之一的差分数据输入连接到另一个缓冲存储元件的内部存储节点，并且脉冲信号可以在内部差分存储节点被分接。
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公开(公告)号：US20090115468A1
公开(公告)日：2009-05-07
申请号：US12090165
申请日：2006-09-28
申请人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
发明人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
IPC分类号： H03L7/00
CPC分类号： H03K3/356156
摘要： An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time.
摘要翻译： 一种集成电路，包括被配置为保留数据的第一数据保持元件，具有第一建立时间的第一数据保持元件和被配置为保留数据的第二数据保持元件，第二数据保持元件具有第二建立时间， 所述第二数据保留元件还具有数据输入。 第二数据保持元件与第一数据保持元件并联连接，并且第二数据保持元件可经由数据输入配置，使得第二建立时间比第一建立时间长。
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