公开(公告)号：US20240163141A1

公开(公告)日：2024-05-16

申请号：US18388395

申请日：2023-11-09

Applicant: ROHM CO., LTD.

Inventor： Kei NAGAO

IPC: H04L25/40 ,  H04L12/40

CPC classification number: H04L25/40 ,  H04L12/40058 ,  H04L2012/40215

Abstract: A semiconductor device includes a reception data input terminal configured such that reception data, which is serial data, is input; a transmission data output terminal configured such that transmission data, which is serial data, is output; and a communication part configured to receive the reception data and transmit the transmission data, wherein the communication part includes: a counter; and a synchronization part configured to monitor the transmission data if the semiconductor device is other than a target device set in the reception data, and reset a count by the counter upon detecting a stop bit and a start bit at frame switching in the transmission data.

公开(公告)号：US20140355700A1

公开(公告)日：2014-12-04

申请号：US14462560

申请日：2014-08-18

Applicant: Keyssa, Inc.

Inventor： Gary D. McCormack ,  Ian A. Kyles

IPC: H04L25/40

CPC classification number: H04L25/40 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49861 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01Q1/2283 ,  H01Q7/00 ,  H01Q9/26 ,  H04L7/0087 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A system for communicating modulated EHF signals may include a modulation circuit responsive to a bi-level transmit information signal for generating a transmit output signal. The transmit output signal may have an EHF frequency when the transmit information signal is at a first information state and may be suppressed when the transmit information signal is at a second information state. A transmit transducer operatively coupled to the modulation circuit may be responsive to the transmit output signal for converting the transmit output signal into an electromagnetic signal.

Abstract translation: 用于传送调制的EHF信号的系统可以包括响应于双电平发射信息信号的调制电路，用于产生发射输出信号。 当发送信息信号处于第一信息状态时，发送输出信号可以具有EHF频率，并且当发送信息信号处于第二信息状态时可以抑制发送输出信号。 可操作地耦合到调制电路的发射传感器可以响应于发射输出信号，以将发射输出信号转换成电磁信号。

公开(公告)号：US08842492B2

公开(公告)日：2014-09-23

申请号：US13823866

申请日：2011-11-19

Applicant: Ian Shaeffer ,  Frederick A. Ware ,  Scott C. Best

Inventor： Ian Shaeffer ,  Frederick A. Ware ,  Scott C. Best

IPC: G11C8/00 ,  H04L25/40 ,  G06F13/00 ,  G11C7/22

CPC classification number: H04L25/40 ,  G06F13/00 ,  G06F13/1689 ,  G11C7/22 ,  Y02D10/14

Abstract: Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.

Abstract translation: 呈现了在各种实施例中以相同频率循环的多个定时参考信号（例如，时钟信号）以飞越拓扑分布到多个存储器件。 这些多个时钟信号各自具有彼此不同的相位关系（例如，正交）。 第一电路接收这些时钟中的第一个作为第一定时参考信号。 第二电路接收这些时钟中的第二时钟作为第二定时参考信号。 多个接收器电路相对于第一定时参考信号和第二定时参考信号同步地接收信号，使得使用第一定时参考信号来解析第一信号值，并且使用第二定时参考信号来解析第二信号值 。

公开(公告)号：US20140211894A1

公开(公告)日：2014-07-31

申请号：US13997291

申请日：2012-05-31

Applicant: INTEL CORPORATON

Inventor： Wei-Lien Yang

IPC: H04L25/40

CPC classification number: H04L25/40 ,  H03M9/00 ,  H04L25/4902

Abstract: In one embodiment, an apparatus may include a de-serializer to convert serial data to parallel data, and a counter to provide an update signal based on a bit count of the serial data. The apparatus may further include a synchronizer to provide a synchronization signal when a target clock signal is synchronized with the update signal. The apparatus may further include an output unit to provide a validation indicator in response to the synchronization signal.

Abstract translation: 在一个实施例中，装置可以包括将串行数据转换为并行数据的解串器，以及用于基于串行数据的位计数来提供更新信号的计数器。 该装置还可以包括同步器，用于当目标时钟信号与更新信号同步时提供同步信号。 该装置还可以包括输出单元，以响应于同步信号提供确认指示符。

公开(公告)号：US07936792B2

公开(公告)日：2011-05-03

申请号：US11063196

申请日：2005-02-22

Applicant: Masahiro Yoshimoto

Inventor： Masahiro Yoshimoto

IPC: H04J3/06

CPC classification number: H04L25/40 ,  H04L25/38

Abstract: The present invention relates to serial asynchronous transmission of data of fixed length in which a start bit and a stop bit are inserted at the head and tail, respectively, of the data. The insertion of a fixed bit having a predetermined logical value every predetermined number of bits of the data allows an idle state period to be reduced up to the predetermined number of bits plus 1 bit, resulting in considerable improvement in transmission efficiency.

Abstract translation: 本发明涉及固定长度的数据的串行异步传输，其中起始位和停止位分别插入数据的头部和尾部。 每隔预定数量的位数插入具有预定逻辑值的固定位允许将空闲状态周期减少到预定位数加上1位，导致传输效率显着提高。

公开(公告)号：US20100231288A1

公开(公告)日：2010-09-16

申请号：US12597239

申请日：2008-04-23

Applicant: Wolfgang Horn

Inventor： Wolfgang Horn

IPC: H03H11/00

CPC classification number: H03K19/0016 ,  H04L25/0292 ,  H04L25/40

Abstract: The present invention relates to a LIN receiver having sleep/wake-up functionality, which has an input (LINI) to a LIN bus (LIN), an output (RXDO), terminals for at least one supply voltage (BVDD), and transistors (M1 through M17), the transistors (M1 through M17) being switched to activate the receiver in the recessive state of the LIN bus via a state change on the LIN bus into an active state of the receiver. In particular, the input (LINI) is connected between components of a voltage-to-current converter (SSW), in particular between a first and a second resistors, (R2, R2).

Abstract translation: 本发明涉及具有睡眠/唤醒功能的LIN接收机，其具有到LIN总线（LIN）的输入（LINI），输出（RXDO），至少一个电源电压（BVDD）的端子和晶体管 （M1至M17），晶体管（M1至M17）被切换，以使LIN总线的隐性状态下的接收器经由LIN总线上的状态改变激活到接收器的有效状态。 特别地，输入（LINI）连接在电压 - 电流转换器（SSW）的组件之间，特别是在第一和第二电阻器（R2，R2）之间。

公开(公告)号：US20090180580A1

公开(公告)日：2009-07-16

申请号：US12382167

申请日：2009-03-10

Applicant: Kazuhiro Sakai ,  Kazuhiro Suzuki ,  Tomo Baba ,  Tsutomu Hamada ,  Shinobu Ozeki ,  Masaru Kijima ,  Masaaki Miura ,  Takeshi Kamimura ,  Yoshihide Sato

Inventor： Kazuhiro Sakai ,  Kazuhiro Suzuki ,  Tomo Baba ,  Tsutomu Hamada ,  Shinobu Ozeki ,  Masaru Kijima ,  Masaaki Miura ,  Takeshi Kamimura ,  Yoshihide Sato

IPC: H04L7/00

CPC classification number: H04L25/242 ,  H04J3/0629 ,  H04L7/0033 ,  H04L7/0337 ,  H04L7/042 ,  H04L7/10 ,  H04L25/40

Abstract: For signals to be transmitted through a signal transmission path constituted by a relay device group for relay for each set of a plurality of channels, a timing adjustment unit is provided in both or one of a receiver-side LSI and a transmitter-side LSI for each set of a plurality of channels transmitted through the relay device group for relay so that the signals can be transmitted with accurate timing. In addition, the timing adjustment unit can adjust the timing for signals transmitted through each relay device group, the timing in one receiver-side LSI in signal transmission through a plurality of relay device groups, and the timing in one-to-many signal transmission in which signals are transmitted from one transmitter-side LSI to a plurality of receiver-side LSIs.

公开(公告)号：US20080278240A1

公开(公告)日：2008-11-13

申请号：US12117997

申请日：2008-05-09

Applicant: Philippe Sirito-Olivier ,  Pietro Calo ,  Mario Chiricosta

Inventor： Philippe Sirito-Olivier ,  Pietro Calo ,  Mario Chiricosta

IPC: H03G3/20 ,  H03G3/00

CPC classification number: H03K5/08 ,  H03K5/1252 ,  H04L25/062 ,  H04L25/40

Abstract: Receiving circuitry having a plurality of amplifiers coupled in series, a first of the amplifiers receiving an input signal and each of the amplifiers outputting an amplified signal; a plurality of comparators each coupled to the output of one of the amplifiers and having an input for receiving the amplified signal; signal identification circuitry coupled to the outputs of the comparators and arranged to determine whether the outputs of the comparators validly represent data; and signal selection circuitry arranged to select the best signal originating from the comparators based on the validity of the outputs of the comparators.

Abstract translation: 接收电路具有串联耦合的多个放大器，第一放大器接收输入信号，并且每个放大器输出放大信号; 多个比较器，每个比较器分别耦合到一个放大器的输出，并具有用于接收放大的信号的输入; 信号识别电路，耦合到比较器的输出，并被布置成确定比较器的输出是否有效地表示数据; 以及信号选择电路，其被布置为基于比较器的输出的有效性来选择源自比较器的最佳信号。

公开(公告)号：US20070201104A1

公开(公告)日：2007-08-30

申请号：US11676747

申请日：2007-02-20

Applicant: Hideyuki KIHARA

Inventor： Hideyuki KIHARA

IPC: H04N1/00

CPC classification number: H04L25/40

Abstract: A data receiving apparatus which makes it possible to obtain reliable received data during EOP period and a preceding period, and which makes it possible to receive serial data in a reliable manner. Data receiving apparatus 100 is provided with receiving comparator 102 which has first signal line 101a and second signal line 101b for differential input; NOR circuit 105 that outputs a logical output, as a trigger signal, at the time the first signal and the second signal have changed from out-of-phase to in-phase; and D-FF circuit 107 that retrieves, by means of a trigger signal from NOR circuit 105, and holds an output RCV of receiving comparator 102; wherein selection circuit 108 selects the output of receiving comparator 102, when the first signal of first signal line 101a and the second signal of second signal line 101b are out-of-phase with each other, and outputs, as received data, a value held in D-FF circuit, when the first signal and the second signal have changed from out-of-phase to in-phase.

Abstract translation: 一种数据接收装置，其可以在EOP周期和前一时段期间获得可靠的接收数据，并且使得可以以可靠的方式接收串行数据。 数据接收装置100设置有接收比较器102，其具有用于差分输入的第一信号线101a和第二信号线101b; NOR电路105，其在第一信号和第二信号从异相变为同相时输出作为触发信号的逻辑输出; 和D-FF电路107，其通过来自或非电路105的触发信号检索并保持接收比较器102的输出RCV; 其中当第一信号线101a的第一信号和第二信号线101b的第二信号彼此不同相时，选择电路108选择接收比较器102的输出，并将其作为接收数据输出 当第一信号和第二信号从异相变为同相时，保持在D-FF电路中的值。

公开(公告)号：US20020172315A1

公开(公告)日：2002-11-21

申请号：US09860229

申请日：2001-05-17

Inventor： Terence Sean Sullivan

IPC: H04L023/00 ,  H04L025/38

CPC classification number: H04L25/40 ,  H04L25/0262

Abstract: A method and apparatus for determining the appropriate timing interval for each bit or data symbol in serial data communications. A sending device transmits a predetermined bit sequence, such as a binary pattern corresponding to one byte, either on its own initiative or in response to an action of a receiving device. A microprocessor in the receiving device measures a calibration time interval between the leading edge of a start bit and a subsequent marker transition, either between subsequent data bits or between the final data bit and the stop bit. This measured interval may be mathematically converted to units useful to calibrate a function or device that conducts input/output operations. Optionally, the process may be repeated periodically to compensate for clock rate drift. This invention may be used for autobaud data rate detection, or matching the actual data rate of a remote serial device, and permits accurate communications without precision timing references.

Abstract translation: 一种用于在串行数据通信中确定每个位或数据符号的适当定时间隔的方法和装置。 发送装置主要或响应于接收装置的动作，发送预定比特序列，例如对应于一个字节的二进制模式。 接收装置中的微处理器测量在后续数据位之间或在最终数据位和停止位之间的起始位的前沿和后续标记转换之间的校准时间间隔。 该测量的间隔可以被数学地转换成用于校准进行输入/输出操作的功能或装置的单元。 可选地，可以周期性地重复该过程以补偿时钟速率漂移。 本发明可以用于自动波特率数据速率检测，或者匹配远程串行设备的实际数据速率，并且允许精确的通信而没有精确的定时参考。