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公开(公告)号：US20230063479A1
公开(公告)日：2023-03-02
申请号：US17405626
申请日：2021-08-18
发明人： Jia-Hong GAO , Hui-Zhong ZHUANG
IPC分类号： G06F30/392 , H01L21/04
摘要： An integrated circuit (IC) includes a first, second and third semiconductor cell regions. The first cell region includes a first active region having a first dopant type. The second semiconductor cell region abuts the first cell region in a second direction, and includes second and third active regions having correspondingly a second dopant type and the first dopant type. The second active region is between the first and third active regions. The third cell region abuts the second cell region in the second direction, and includes a fourth active region having the second dopant type. The third active region is between the fourth active region and the second active region. The second semiconductor cell region has a height 2H, and the first, second and third semiconductor cell regions collectively have a height 3H.
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公开(公告)号：US20230067734A1
公开(公告)日：2023-03-02
申请号：US17462974
申请日：2021-08-31
IPC分类号： H01L27/02 , H01L23/528 , G06F30/392 , H01L27/118 , H01L23/522 , H01L21/768
摘要： An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.
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公开(公告)号：US20240274592A1
公开(公告)日：2024-08-15
申请号：US18333405
申请日：2023-06-12
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L29/40 , H01L29/66
CPC分类号： H01L27/0207 , H01L27/0617 , H01L27/0928 , H01L29/401 , H01L29/66568
摘要： A cell region of a semiconductor device includes: active regions (ARs) formed as predetermined shapes on a substrate including first and second ARs having a first shape and correspondingly first and second dopant types, a third AR having a second shape and the second dopant type, and a fourth AR having a third shape and the first dopant type. The first and second ARs are arranged in a first area of the cell region. The third and fourth ARs are arranged in a second area of the cell region. The second area is adjacent to the first area relative to a first direction (e.g., Y-axis (vertical adjacency-architecture) or X-axis (horizontal adjacency-architecture)). The first shape is smaller than the second shape. The second shape is smaller than the third shape.
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公开(公告)号：US20240038762A1
公开(公告)日：2024-02-01
申请号：US18314536
申请日：2023-05-09
发明人： Hui-Zhong ZHUANG , Johnny Chiahoa LI , Tzu-Ying LIN , Jia-Hong GAO , Jung-Chan YANG , Jerry Chang Jui KAO
IPC分类号： H01L27/118 , H01L27/02 , H01L21/8238 , H03K3/037
CPC分类号： H01L27/11807 , H01L27/0207 , H01L21/82385 , H01L21/823871 , H03K3/037 , H01L2027/11837 , H01L2027/11866
摘要： A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.
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公开(公告)号：US20240250671A1
公开(公告)日：2024-07-25
申请号：US18624868
申请日：2024-04-02
IPC分类号： H03K3/3562 , H03K3/012 , H03K3/037 , H03K3/356
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/0372 , H03K3/356104
摘要： An integrated circuit (IC) device includes a master latch circuit having a data output, a slave latch circuit having a data input electrically coupled to the data output of the master latch circuit, and a clock circuit electrically coupled to the master latch circuit and the slave latch circuit. The slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.
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公开(公告)号：US20230409798A1
公开(公告)日：2023-12-21
申请号：US18448115
申请日：2023-08-10
发明人： Jia-Hong GAO , Hui-Zhong ZHUANG
IPC分类号： G06F30/392 , H01L21/04 , H01L21/02 , H01J37/305
CPC分类号： G06F30/392 , H01L21/041 , H01L21/02 , H01J37/3056
摘要： A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.
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公开(公告)号：US20230268910A1
公开(公告)日：2023-08-24
申请号：US17825704
申请日：2022-05-26
IPC分类号： H03K3/3562 , H03K3/012 , H03K3/037
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/0372
摘要： An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.
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