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公开(公告)号：US20230411378A1
公开(公告)日：2023-12-21
申请号：US18363230
申请日：2023-08-01
IPC分类号： H01L27/02 , G06F1/3287
CPC分类号： H01L27/0207 , G06F1/3287
摘要： An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.
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公开(公告)号：US20230378267A1
公开(公告)日：2023-11-23
申请号：US18358694
申请日：2023-07-25
IPC分类号： H01L29/06 , H01L27/092 , H01L27/02 , H01L21/033 , H01L29/66 , H01L29/78 , H01L21/8238 , G06F30/392
CPC分类号： H01L29/0696 , H01L27/0924 , H01L27/0207 , H01L21/0337 , H01L29/6681 , H01L29/7851 , H01L21/823821 , H01L29/66545 , G06F30/392
摘要： A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.
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公开(公告)号：US20230060387A1
公开(公告)日：2023-03-02
申请号：US18053012
申请日：2022-11-07
发明人： Pochun WANG , Ting-Wei CHIANG , Chih-Ming LAI , Hui-Zhong ZHUANG , Jung-Chan YANG , Ru-Gun LIU , Ya-Chi CHOU , Yi-Hsiung LIN , Yu-Xuan HUANG , Yu-Jung CHANG , Guo-Huei WU , Shih-Ming CHANG
IPC分类号： H01L23/535 , H01L21/768 , H01L27/088 , H01L27/092 , H01L21/8238 , G06F30/39 , G06F30/392
摘要： An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.
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公开(公告)号：US20220382951A1
公开(公告)日：2022-12-01
申请号：US17885118
申请日：2022-08-10
发明人： Jung-Chan YANG , Ting-Wei CHIANG , Jerry Chang-Jui KAO , Hui-Zhong ZHUANG , Lee-Chung LU , Li-Chun TIEN , Meng-Hung SHEN , Shang-Chih HSIEH , Chi-Yu LU
IPC分类号： G06F30/394 , H01L27/118 , H01L23/522 , H01L23/528 , H01L27/02
摘要： A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
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公开(公告)号：US20220068816A1
公开(公告)日：2022-03-03
申请号：US17220345
申请日：2021-04-01
发明人： Jung-Chan YANG , Chi-Yu LU , Hui-Zhong ZHUANG , Chih-Liang CHEN
IPC分类号： H01L23/535 , H01L29/417 , H01L29/40 , H01L21/768
摘要： A semiconductor device including: an active region; first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction and correspondingly overlap the active region; a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, and overlaps the first, second and third MD contact structures; a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and, relative to the second direction, overlaps each of the first, second and third MD contact structures; and a first via-to-MD (VD) structure between the first MD contact structure and the first conductive segment, the first VD structure electrically coupling the first conductive segment, the V2V rail and the first MD contact structure; wherein at least one of the second or third MD contact structures is electrically decoupled from the V2V rail.
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公开(公告)号：US20210326511A1
公开(公告)日：2021-10-21
申请号：US17362170
申请日：2021-06-29
发明人： Jian-Sing LI , Jung-Chan YANG , Ting Yu CHEN , Ting-Wei CHIANG
IPC分类号： G06F30/394 , G06F30/392
摘要： A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.
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公开(公告)号：US20240332174A1
公开(公告)日：2024-10-03
申请号：US18739834
申请日：2024-06-11
发明人： Cheng-Yu LIN , Jung-Chan YANG , Hui-Zhong ZHUANG , Sheng-Hsiung CHEN , Kuo-Nan YANG , Chih-Liang CHEN , Lee-Chung LU
IPC分类号： H01L23/528 , G06F30/347 , G06F30/392 , G06F30/394 , H01L23/50 , H01L27/02 , H01L27/07 , H01L27/118 , H01L29/417
CPC分类号： H01L23/528 , G06F30/347 , G06F30/392 , G06F30/394 , H01L23/50 , H01L27/07 , H01L27/11807 , H01L29/41733 , H01L27/0207 , H01L2027/11879 , H01L2027/11881 , H01L2027/11887
摘要： An IC device includes first and second circuits adjacent each other and over a substrate. The first circuit includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second circuit includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second circuit or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connecting the first IO pattern and a second IO pattern of the second circuit. The second IO pattern is one of the plurality of conductive patterns of the second circuit and is along the first track.
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公开(公告)号：US20240330564A1
公开(公告)日：2024-10-03
申请号：US18741003
申请日：2024-06-12
发明人： Jung-Chan YANG , Hui-Zhong ZHUANG , Ting-Wei CHIANG , Chi-Yu LU
IPC分类号： G06F30/398 , G03F1/36 , G03F1/70 , G06F30/30 , G06F30/392 , G06F30/394 , G06F30/3953 , G06F119/18
CPC分类号： G06F30/398 , G03F1/36 , G03F1/70 , G06F30/30 , G06F30/392 , G06F30/394 , G06F30/3953 , G06F2119/18
摘要： A semiconductor device includes a plurality of active regions extending in a first direction. The semiconductor device further includes a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction. The semiconductor device further includes a power rail extending in the first direction. The power rail includes a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.
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公开(公告)号：US20230124119A1
公开(公告)日：2023-04-20
申请号：US18066154
申请日：2022-12-14
IPC分类号： H01L27/02 , G06F1/3287
摘要： An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.
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公开(公告)号：US20210350062A1
公开(公告)日：2021-11-11
申请号：US17383153
申请日：2021-07-22
发明人： Jung-Chan YANG , Hui-Zhong ZHUANG , Ting-Wei CHIANG , Chi-Yu LU
IPC分类号： G06F30/398 , G03F1/70 , G03F1/36 , G06F30/30 , G06F30/3953
摘要： An integrated circuit includes at least one source/drain (S/D) line extending in second direction in a cell of the integrated circuit. The integrated circuit further includes a conductive element extending in a first direction in the cell of the integrated circuit, the first direction being perpendicular to the second direction. The integrated circuit further includes a power rail extending over the conductive element, wherein the power rail includes a first power rail portion and a second power rail portion, and an inner edge of the first power rail portion is offset from an inner edge of the second power rail portion, wherein the first power rail portion has a first edge and the second power rail portion has a second edge on the same side as the first edge of the first power rail portion, and the first edge and the second edge are laterally separated.
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