公开(公告)号：US11831285B2

公开(公告)日：2023-11-28

申请号：US17077771

申请日：2020-10-22

Applicant: M31 TECHNOLOGY CORPORATION

Inventor： Ching-Hsiang Chang

IPC: H04B1/10 ,  H03F3/45 ,  H03K3/038 ,  H03K19/0175 ,  H03K19/0185 ,  H04B1/04 ,  H04B1/16 ,  H04N7/04

CPC classification number: H03F3/45179 ,  H03K3/038 ,  H03K19/017509 ,  H03K19/018528 ,  H04B1/04 ,  H04B1/16 ,  H04N7/04

Abstract: A driver circuit includes a first output terminal, a first switch, a second switch, a third switch and a power source. The first output terminal is arranged for outputting a data output. The first switch is selectively coupled between the first output terminal and a power supply node according to a data input. The second switch is selectively coupled between the first output terminal and a first reference node according to the data input. The third switch is selectively coupled between the first reference node and a reference voltage. The power source is configured to selectively provide one of a supply voltage signal and a supply current signal to the power supply node. When the power source is configured to provide the supply voltage signal, the third switch is switched on. When the power source is configured to provide the supply current signal, the third switch is switched off.

公开(公告)号：US20220224316A1

公开(公告)日：2022-07-14

申请号：US17711638

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

IPC: H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

公开(公告)号：US10886882B2

公开(公告)日：2021-01-05

申请号：US16264928

申请日：2019-02-01

Applicant: M31 TECHNOLOGY CORPORATION

Inventor： Ching-Hsiang Chang

IPC: H03F3/45 ,  H03K3/038 ,  H04B1/04 ,  H04B1/16 ,  H04N7/04

Abstract: A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.

公开(公告)号：US10158348B1

公开(公告)日：2018-12-18

申请号：US15886652

申请日：2018-02-01

Applicant: Alexander L. Braun

Inventor： Alexander L. Braun

IPC: H01L39/22 ,  H01L39/02 ,  H03K19/195 ,  H03K3/038 ,  G11C11/44 ,  H01L39/04 ,  H01L39/24

Abstract: A tri-stable storage loop useful in reciprocal quantum logic (RQL) gate circuits and systems has control and signal input lines. When alternating stable current storage states are induced in the storage loop by an alternating input provided to the control input line, provision of a positive SFQ pulse on the signal input line while the storage loop stores a positive current changes the storage loop from alternating between a positive-current state and a null-current state to alternating between a negative-current state and the null-current state, and provision of a negative SFQ pulse on the signal input line while the storage loop stores a negative current changes the storage loop from alternating between the negative-current state and the null-current state to alternating between the positive-current state and the null-current state.

公开(公告)号：US10110203B2

公开(公告)日：2018-10-23

申请号：US15454405

申请日：2017-03-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Navneet Gupta ,  Adam Makosiej ,  Costin Anghel ,  Amara Amara

IPC: H03K3/3562 ,  H03K19/00 ,  H03K3/012 ,  H03K3/038 ,  H03K19/094

Abstract: Tri-state inverter includes a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter, and a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero, wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.

公开(公告)号：US10009027B2

公开(公告)日：2018-06-26

申请号：US15476847

申请日：2017-03-31

Applicant: Nvidia Corporation

Inventor： Andreas J. Gotterba ,  Jesse S. Wang

IPC: H03K19/00 ,  H03K3/038 ,  H03K19/094 ,  G11C11/419 ,  G11C7/06

CPC classification number: H03K19/0002 ,  G11C7/065 ,  G11C11/419 ,  H03K3/038 ,  H03K19/09425

Abstract: Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n−1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

公开(公告)号：US3437832A

公开(公告)日：1969-04-08

申请号：US3437832D

申请日：1966-05-23

Applicant: NASA

Inventor： KOPETSKI FREDERICK J

IPC: H03K3/038 ,  H03K23/08

CPC classification number: H03K3/038

公开(公告)号：US3184612A

公开(公告)日：1965-05-18

申请号：US22977162

申请日：1962-10-10

Applicant: PETERSEN EARL J

Inventor： PETERSEN EARL J

IPC: H03K3/038 ,  H03K3/30 ,  H03K5/15

CPC classification number: H03K5/15093 ,  H03K3/038 ,  H03K3/30

公开(公告)号：US3047738A

公开(公告)日：1962-07-31

申请号：US74149158

申请日：1958-06-12

Applicant: BELL TELEPHONE LABOR INC

Inventor： HAAS JR CHARLES W

IPC: H03K3/038

CPC classification number: H03K3/038

公开(公告)号：US20250062753A1

公开(公告)日：2025-02-20

申请号：US18749575

申请日：2024-06-20

Applicant: DigWise Technology Corporation, LTD

Inventor： Hung-Lin Wu ,  Chih-Wen Yang ,  Yu-Chen Lo

IPC: H03K3/038

Abstract: A control device includes multi-stage control circuits. An i-th stage control circuit includes an input signal generator and an acknowledge signal generator. The input signal generator generates an i+1-th stage input signal according to a first inverted output signal and an i+1-th stage acknowledge signal. The acknowledge signal generator generates an i-th stage acknowledge signal according to an i-th stage delayed input signal and a second inverted output signal, wherein i is an integer larger than 1. Phases of the first inverted output signal and the second inverted output signal are opposite to a phase of an i-th stage output signal generated by an i-th stage pulse signal generator.