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公开(公告)号：US20230352060A1
公开(公告)日：2023-11-02
申请号：US18221111
申请日：2023-07-12
发明人： Nan-Chun LIEN , Li-Wei CHU , Ting-Wei CHANG
CPC分类号： G11C5/025 , G11C7/1084 , G11C7/1057
摘要： A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.
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公开(公告)号：US11742000B2
公开(公告)日：2023-08-29
申请号：US17521894
申请日：2021-11-09
发明人： Nan-Chun Lien , Li-Wei Chu , Ting-Wei Chang
CPC分类号： G11C5/025 , G11C7/1057 , G11C7/1084
摘要： A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.
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公开(公告)号：US20230040348A1
公开(公告)日：2023-02-09
申请号：US17521894
申请日：2021-11-09
发明人： Nan-Chun LIEN , Li-Wei CHU , Ting-Wei CHANG
摘要： A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.
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公开(公告)号：US11418209B2
公开(公告)日：2022-08-16
申请号：US17223933
申请日：2021-04-06
发明人： Hui Huan Wang , Meng Hsuan Wu
摘要： A signal conversion circuit includes a first pair of capacitors and a comparator. The first pair of capacitors includes a first capacitor and a second capacitor having a same capacitance value. Each of the first capacitor and the second capacitor is coupled to an input signal during a first sampling phase, while uncoupled from the input signal during a first conversion phase after the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal, and the comparator is configured to compare a signal level at the first input terminal and a signal level at the second input terminal to convert the input signal.
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5.发明申请公开(公告)号：US20210399735A1
公开(公告)日：2021-12-23
申请号：US17355181
申请日：2021-06-23
发明人： HUI HUAN WANG , MENG HSUAN WU
摘要： A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.
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公开(公告)号：US20210311512A1
公开(公告)日：2021-10-07
申请号：US17223905
申请日：2021-04-06
发明人： CHING-HSIANG CHANG , YU-HSUN CHIEN
摘要： A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.
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公开(公告)号：US20210067113A1
公开(公告)日：2021-03-04
申请号：US17077771
申请日：2020-10-22
发明人： CHING-HSIANG CHANG
摘要： A driver circuit includes a first output terminal, a first switch, a second switch, a third switch and a power source. The first output terminal is arranged for outputting a data output. The first switch is selectively coupled between the first output terminal and a power supply node according to a data input. The second switch is selectively coupled between the first output terminal and a first reference node according to the data input. The third switch is selectively coupled between the first reference node and a reference voltage. The power source is configured to selectively provide one of a supply voltage signal and a supply current signal to the power supply node. When the power source is configured to provide the supply voltage signal, the third switch is switched on. When the power source is configured to provide the supply current signal, the third switch is switched off.
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公开(公告)号：US10795767B2
公开(公告)日：2020-10-06
申请号：US16233034
申请日：2018-12-26
发明人： Zhi-Xian Chou , Wei-Chiang Shih
IPC分类号： G06F11/10 , G06F11/00 , G11C11/419
摘要： An error correcting system is provided. The error correcting system includes an error correcting code (ECC) circuit and a control circuit. The ECC circuit is configured to encode input data received from M input terminals to generate encoded data in response to a write operation, and output the encoded data. The input data includes write data associated with the write operation, and the encoded data includes the input data and associated parity data. The control circuit is coupled to at least one of the M input terminals. When the write operation is directed to a memory device having a data bit width less than M bits, the write data is inputted to a portion of the M input terminals, the control circuit is configured to provide reference data to another portion of the M input terminals, and the write data and the reference data serve as the input data.
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公开(公告)号：US10574431B2
公开(公告)日：2020-02-25
申请号：US16262861
申请日：2019-01-30
IPC分类号： H03M13/00 , H04L7/00 , H03K19/21 , H03K3/037 , H03K7/08 , G04F10/00 , H03F3/45 , G06F1/06 , H03K5/14 , H03K5/156 , G09G3/20 , H04L25/02 , G09G5/00 , H03M7/00 , H04M1/38 , H04B1/40 , H04B1/58 , H04B3/00 , H04B1/00
摘要： A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.
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10.发明申请公开(公告)号：US20190138488A1
公开(公告)日：2019-05-09
申请号：US15805098
申请日：2017-11-06
发明人： Pin-Hao Feng , Yueh-Chuan Lu , Ching-Hsiang Chang
CPC分类号： G06F13/4282 , G06F1/10
摘要： An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.
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