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公开(公告)号：US10574431B2
公开(公告)日：2020-02-25
申请号：US16262861
申请日：2019-01-30
IPC分类号： H03M13/00 , H04L7/00 , H03K19/21 , H03K3/037 , H03K7/08 , G04F10/00 , H03F3/45 , G06F1/06 , H03K5/14 , H03K5/156 , G09G3/20 , H04L25/02 , G09G5/00 , H03M7/00 , H04M1/38 , H04B1/40 , H04B1/58 , H04B3/00 , H04B1/00
摘要： A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.
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公开(公告)号：US10263762B2
公开(公告)日：2019-04-16
申请号：US16039348
申请日：2018-07-19
IPC分类号： G06F5/00 , H04L7/00 , H03K19/21 , H03K3/037 , H03K7/08 , G04F10/00 , H03F3/45 , G06F1/06 , H03K5/14 , H03M7/00 , H04M1/38 , H04B1/40 , H04B1/58 , H04B3/00 , H04B1/00
摘要： The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).
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公开(公告)号：US20190165925A1
公开(公告)日：2019-05-30
申请号：US16262861
申请日：2019-01-30
IPC分类号： H04L7/00 , H03K3/037 , G04F10/00 , H03F3/45 , G06F1/06 , H03K19/21 , H03K5/156 , H03K7/08 , H03K5/14
CPC分类号： H04L7/0016 , G04F10/005 , G06F1/06 , G09G3/20 , G09G5/003 , G09G2370/08 , H03F3/45475 , H03F2200/129 , H03F2203/45116 , H03F2203/45594 , H03K3/037 , H03K5/14 , H03K5/1565 , H03K7/08 , H03K19/21 , H03M7/00 , H04B1/00 , H04B1/40 , H04B1/581 , H04B3/00 , H04L25/0272 , H04L25/0292 , H04L25/0298 , H04M1/38
摘要： A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.
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公开(公告)号：US20180323952A1
公开(公告)日：2018-11-08
申请号：US16039348
申请日：2018-07-19
CPC分类号： H04L7/0016 , G04F10/005 , G06F1/06 , H03F3/45475 , H03F2200/129 , H03F2203/45116 , H03F2203/45594 , H03K3/037 , H03K5/14 , H03K5/1565 , H03K7/08 , H03K19/21 , H03M7/00 , H04B1/00 , H04B1/40 , H04B1/581 , H04B3/00 , H04M1/38
摘要： The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).
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5.发明申请公开(公告)号：US20180241382A1
公开(公告)日：2018-08-23
申请号：US15616937
申请日：2017-06-08
发明人： Huai-Te Wang , Chih Chien Hung
IPC分类号： H03K5/1252 , H01B11/00 , G06F13/40
CPC分类号： H03K5/1252 , G06F13/4027 , G06F13/4072 , H04B3/02 , H04L25/00
摘要： A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.
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公开(公告)号：US11936388B2
公开(公告)日：2024-03-19
申请号：US18146854
申请日：2022-12-27
发明人： Guo-Hau Lee , Huai-Te Wang , Cheng-Liang Hung
CPC分类号： H03L7/0807 , H03K3/037 , H03L7/0893 , H03L7/091 , H03L7/0992 , H03L7/0995 , H03L7/189 , H03M1/38
摘要： A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
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公开(公告)号：US11569822B2
公开(公告)日：2023-01-31
申请号：US17355178
申请日：2021-06-23
发明人： Guo-Hau Lee , Huai-Te Wang , Cheng-Liang Hung
摘要： A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
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公开(公告)号：US10333505B2
公开(公告)日：2019-06-25
申请号：US15616937
申请日：2017-06-08
发明人： Huai-Te Wang , Chih Chien Hung
IPC分类号： H03K5/1252 , G06F13/40 , H04L25/00 , H04B3/02
摘要： A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.
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