公开(公告)号：US11418209B2

公开(公告)日：2022-08-16

申请号：US17223933

申请日：2021-04-06

申请人： M31 TECHNOLOGY CORPORATION

发明人： Hui Huan Wang ,  Meng Hsuan Wu

IPC分类号： H03M1/12 ,  H03M1/46 ,  G05F1/46 ,  H04B1/40 ,  H03L7/08 ,  H03L7/089 ,  H04L7/033

摘要： A signal conversion circuit includes a first pair of capacitors and a comparator. The first pair of capacitors includes a first capacitor and a second capacitor having a same capacitance value. Each of the first capacitor and the second capacitor is coupled to an input signal during a first sampling phase, while uncoupled from the input signal during a first conversion phase after the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal, and the comparator is configured to compare a signal level at the first input terminal and a signal level at the second input terminal to convert the input signal.

公开(公告)号：US11962308B2

公开(公告)日：2024-04-16

申请号：US18213089

申请日：2023-06-22

申请人： M31 TECHNOLOGY CORPORATION

发明人： Hui Huan Wang ,  Meng Hsuan Wu

IPC分类号： H03M1/38 ,  H03K3/037 ,  H03L7/08 ,  H03L7/089 ,  H03L7/091 ,  H03L7/099 ,  H03L7/189

CPC分类号： H03L7/0807 ,  H03K3/037 ,  H03L7/0893 ,  H03L7/091 ,  H03L7/0992 ,  H03L7/0995 ,  H03L7/189 ,  H03M1/38

摘要： A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.

公开(公告)号：US11736109B2

公开(公告)日：2023-08-22

申请号：US17355181

申请日：2021-06-23

申请人： M31 TECHNOLOGY CORPORATION

发明人： Hui Huan Wang ,  Meng Hsuan Wu

IPC分类号： H03M1/38 ,  H03L7/08 ,  H03L7/189 ,  H03L7/091 ,  H03L7/099 ,  H03L7/089 ,  H03K3/037

CPC分类号： H03L7/0807 ,  H03K3/037 ,  H03L7/0893 ,  H03L7/091 ,  H03L7/0992 ,  H03L7/0995 ,  H03L7/189 ,  H03M1/38

摘要： A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.