公开(公告)号：US20240297639A1

公开(公告)日：2024-09-05

申请号：US18646600

申请日：2024-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Chia LAI ,  Meng-Hung SHEN ,  Chi-Lin LIU ,  Stefan RUSU ,  Yan-Hao CHEN ,  Jerry Chang-Jui KAO

IPC分类号： H03K3/012 ,  H03K3/0233 ,  H03K3/037 ,  H03K3/289 ,  H03K3/356 ,  H03K3/3562

CPC分类号： H03K3/012 ,  H03K3/02332 ,  H03K3/0372 ,  H03K3/289 ,  H03K3/356104 ,  H03K3/3562 ,  H03K3/35625

摘要： A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US11942945B2

公开(公告)日：2024-03-26

申请号：US17815156

申请日：2022-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Huaixin Xian ,  Qingchao Meng ,  Yang Zhou ,  Shang-Chih Hsieh

IPC分类号： H01L27/105 ,  H01L29/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H03K3/037 ,  H03K3/288 ,  H03K3/289 ,  H03K3/356 ,  H03K3/3562

CPC分类号： H03K3/0372 ,  H01L27/105 ,  H01L29/02 ,  H01L29/06 ,  H01L29/1075 ,  H01L29/41725 ,  H03K3/288 ,  H03K3/289 ,  H03K3/356017 ,  H03K3/356104 ,  H03K3/356113 ,  H03K3/356147 ,  H03K3/3562 ,  H03K3/35625

摘要： A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.

公开(公告)号：US08836398B2

公开(公告)日：2014-09-16

申请号：US13759240

申请日：2013-02-05

申请人： Texas Instruments Incorporated

发明人： Steven Bartling ,  Sudhanshu Khanna

IPC分类号： H03K3/289 ,  H03K3/012

CPC分类号： H03K3/012 ,  H03K3/289 ,  H03K3/35625

摘要： In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

摘要翻译： 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20140218090A1

公开(公告)日：2014-08-07

申请号：US13759240

申请日：2013-02-05

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Steven Bartling ,  Sudhanshu Khanna

IPC分类号： H03K3/012

CPC分类号： H03K3/012 ,  H03K3/289 ,  H03K3/35625

摘要： In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

公开(公告)号：US20110187430A1

公开(公告)日：2011-08-04

申请号：US12700146

申请日：2010-02-04

申请人： Chien Fu Tang ,  Isaac Y. Chen

发明人： Chien Fu Tang ,  Isaac Y. Chen

IPC分类号： H03K3/289

CPC分类号： H03K3/289

摘要： The present invention discloses a multi-chip module with master-slave analog signal transmission function. The multi-chip module comprises: a master chip having a first setting input pin for receiving an analog setting signal to generate an analog setting in the master chip, and the master chip duplicating the analog setting to output a first analog output; and a first slave chip for receiving the first analog output from the master chip to generate an internal setting of the first slave chip.

摘要翻译： 本发明公开了一种具有主从模拟信号传输功能的多芯片模块。 多芯片模块包括：主芯片，具有第一设置输入引脚，用于接收模拟设置信号以在主芯片中产生模拟设置，主芯片复制模拟设置以输出第一模拟输出; 以及第一从芯片，用于从主芯片接收第一模拟输出以产生第一从芯片的内部设置。

公开(公告)号：US06693457B2

公开(公告)日：2004-02-17

申请号：US10199921

申请日：2002-07-18

申请人： Ronald J. Yepp

发明人： Ronald J. Yepp

IPC分类号： H03K190175

CPC分类号： H03K3/2885 ,  H03K3/012 ,  H03K3/289

摘要： An ultra high speed Emitter Coupled Logic (ECL) flip-flop is provided and a method of operating the same. The ECL flip-flop provides for clock levels that operate at logic levels above the data levels. Since the clock operates at logic levels above the data, the clock experiences level shifts that are less than the level shifts of the data. Therefore, the clock will provide a higher fidelity signal relative to the conventional clock signal. The ECL flip-flop can operate at significantly higher data rates than conventional flip-flop circuitry.

摘要翻译： 提供超高速发射极耦合逻辑（ECL）触发器及其操作方法。 ECL触发器提供在逻辑电平高于数据电平的时钟电平。 由于时钟以高于数据的逻辑电平工作，所以时钟经历的电平偏移小于数据的电平偏移。 因此，时钟将相对于传统的时钟信号提供更高的保真度信号。 ECL触发器可以以比传统触发器电路显着更高的数据速率工作。

公开(公告)号：US4975595A

公开(公告)日：1990-12-04

申请号：US221701

申请日：1988-07-20

申请人： Scott Roberts ,  Daniel Chang

发明人： Scott Roberts ,  Daniel Chang

IPC分类号： H03K3/286 ,  H03K3/2885 ,  H03K3/289

CPC分类号： H03K3/2885 ,  H03K3/289

摘要： A circuit is described for functioning as a transparent latch, a latch where the data is determined by the state of a data signal at the time a signal changes state, a D-type flip-flop, and a scan path element. The mode of operation of the circuit is determined by the condition of respective ones of a set of control signals.

摘要翻译： 描述了用作透明锁存器的电路，其中数据由信号改变状态时的数据信号的状态确定的锁存器，D型触发器和扫描路径元件。 电路的工作模式由一组控制信号中的各个条件决定。

公开(公告)号：US4779009A

公开(公告)日：1988-10-18

申请号：US886828

申请日：1986-07-18

申请人： Hiroyuki Tsunoi ,  Eiji Sugiyama ,  Motohiro Seto

发明人： Hiroyuki Tsunoi ,  Eiji Sugiyama ,  Motohiro Seto

IPC分类号： G11C11/40 ,  H03K3/289 ,  H03K3/284 ,  H03K19/00

CPC分类号： H03K3/289

摘要： In a master-slave type flip-flop circuit including a normal function in a normal mode for flip/flop operation and a scanning function in a scanning mode for testing an integrated circuit, the master-slave type flip-flop circuit comprises: a master stage having a first pair of differential transistors for taking in data, a second pair of differential transistors for latching data taken in to the first pair of differential transistors, a third pair of differential transistors for taking in scanning data, and a fourth pair of differential transistors for activating the second and third pair of differential transistors in the scanning mode; and a slave stage having a first pair of differential transistors for taking in data from the master stage, a second pair of differential transistors for latching data taken in to the first pair of differential transistors, a third pair of differential transistors for latching scanning data, and a fourth pair of differential transistors for activating the first and third pair of differential transistors in the scanning mode.

摘要翻译： 主从型触发电路包括：主从触发器电路，包括用于触发/翻转操作的正常模式的正常功能和用于测试集成电路的扫描模式的扫描功能，主从触发器电路包括：主器件 阶段具有用于接收数据的第一对差分晶体管，用于锁存取入第一对差分晶体管的数据的第二对差分晶体管，用于接收扫描数据的第三对差分晶体管和第四对差分 用于在扫描模式下激活第二和第三对差分晶体管的晶体管; 以及具有用于从主级接收数据的第一对差分晶体管的子级，用于锁存取入第一对差分晶体管的数据的第二对差分晶体管，用于锁存扫描数据的第三对差分晶体管， 以及第四对差分晶体管，用于在扫描模式下激活第一和第三对差分晶体管。

公开(公告)号：US4777388A

公开(公告)日：1988-10-11

申请号：US134582

申请日：1987-12-14

申请人： Glenn F. Widener

发明人： Glenn F. Widener

IPC分类号： H03K3/037 ,  H03K3/2885 ,  H03K3/289 ,  H03K17/16

CPC分类号： H03K3/0375 ,  H03K3/2885 ,  H03K3/289

摘要： A fast latching flip-flop has a transparent latch master section with an input amplifier, an output latch, a current source connected to provide current for the input amplifier and the output latch, and a switch for applying the current from the current source to either the input amplifier or the output latch. A slave section is connected to the output latch to transfer the data from the output latch to the output of the fast latching flip-flop. A delay transistor is inserted between the switch and the input amplifier to add delay in the turn-off of the input amplifier. Additional delay is attained by connecting a plurality of diode-connected transistors to the junction of the delay transistor and the switch. The result is a reduction of the metastable region between the turn-off of the input amplifier and the turn-on of the output latch.

摘要翻译： 快速锁存触发器具有透明锁存器主器件部分，其具有输入放大器，输出锁存器，连接到用于为输入放大器和输出锁存器提供电流的电流源，以及用于将来自电流源的电流施加到任一个 输入放大器或输出锁存器。 从部分连接到输出锁存器，以将数据从输出锁存器传送到快速锁存触发器的输出。 延迟晶体管插在开关和输入放大器之间，以增加输入放大器关断的延迟。 通过将多个二极管连接的晶体管连接到延迟晶体管和开关的结点来实现额外的延迟。 结果是输入放大器的关断与输出锁存器的导通之间的亚稳区域的减小。

公开(公告)号：US4714842A

公开(公告)日：1987-12-22

申请号：US212582

申请日：1980-12-03

申请人： Cornelis M. Hart ,  Arie Slob

发明人： Cornelis M. Hart ,  Arie Slob

IPC分类号： H03F3/185 ,  G11C11/34 ,  G11C11/411 ,  G11C11/413 ,  G11C11/414 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/00 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L27/102 ,  H01L29/47 ,  H01L29/72 ,  H01L29/73 ,  H01L29/872 ,  H03F3/04 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03K3/012 ,  H03K3/288 ,  H03K3/289 ,  H03K19/08 ,  H03K19/091 ,  H04R25/00

CPC分类号： H03K19/091 ,  G11C11/34 ,  G11C11/4113 ,  G11C11/413 ,  G11C11/414 ,  H01L27/00 ,  H01L27/0233 ,  H01L27/04 ,  H01L27/06 ,  H01L27/0821 ,  H01L27/1025 ,  H01L29/72 ,  H03F3/04 ,  H03K19/08 ,  H03K3/012 ,  H03K3/288 ,  H03K3/289 ,  H04R25/00 ,  Y10S148/087

摘要： An "Integrated Injection Logic" integrated circuit in which bias currents are supplied by means of a current injector. The current injector is a multi-layer structure in which current is supplied by means of injection and collection of charge carriers via rectifying junctions, to predetermined zones of the circuit to be biased. Such zones are preferably biased by charge carriers which are collected by such zones from one of the layers of the current injector. The circuit also preferably includes a region for reducing carrier injection from a predetermined zone.

摘要翻译： 集成注入逻辑集成电路，其中通过电流注入器提供偏置电流。 电流注入器是多层结构，其中通过经由整流结点的电荷载体的注入和收集来提供电流到被偏置的电路的预定区域。 这样的区域优选地被电荷载体偏置，电荷载体由电流注入器的一个层从这些区域收集。 电路还优选地包括用于减小从预定区域的载流子注入的区域。