公开(公告)号：US20180351553A1

公开(公告)日：2018-12-06

申请号：US15780242

申请日：2016-11-30

申请人： Vanchip (Tianjin) Technology Co., Ltd.

发明人： Sheng LIN

IPC分类号： H03K19/00 ,  H03K19/21 ,  H03K19/08 ,  H03K19/003

CPC分类号： H03K19/0002 ,  H03K19/00307 ,  H03K19/08 ,  H03K19/212 ,  H04B14/00

摘要： Disclosed is a variable coding method for realizing chip reuse, comprising the following steps: using at least two identical integrated circuit chips, wherein each integrated circuit chip executes different control logic truth tables according to different gating signals; introducing at least one logical control signal as a gating signal; and controlling the logical control signal, so that each integrated circuit chip respectively executes a corresponding control logic truth table. Also disclosed is a communication terminal using the variable coding method for realizing chip reuse. Two or more completely identical integrated circuit chips can be used to realize different logical control functions, thereby simplifying the type of a chip for realizing a system function, and greatly reducing the development costs of an integrated circuit system and the management complexity of a mass production supply chain.

公开(公告)号：US20170194333A1

公开(公告)日：2017-07-06

申请号：US14983682

申请日：2015-12-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Cheng Wu ,  I-Ching Chen

IPC分类号： H01L27/115 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/321 ,  H03K19/08 ,  H01L21/28

CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L21/32115 ,  H01L21/32133 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833 ,  H03K19/08

摘要： An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high κ dielectric layers. A high-κ-last method for manufacturing the IC is also provided.

公开(公告)号：US09583704B2

公开(公告)日：2017-02-28

申请号：US14761319

申请日：2014-01-16

申请人： Helmholtz-Zentrum Dresden-Rossendorf e. V.

发明人： Tiangui You ,  Heidemarie Schmidt ,  Nan Du ,  Danilo Buerger ,  Ilona Skorupa

IPC分类号： H01L45/00 ,  H01L31/0749 ,  H01L27/24 ,  G09C1/00 ,  H04L9/06 ,  H03K19/08 ,  H04L9/00 ,  G11C13/00

CPC分类号： H01L45/147 ,  G09C1/00 ,  G11C13/0007 ,  H01L27/2472 ,  H01L31/0749 ,  H01L45/065 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1641 ,  H01L45/165 ,  H03K19/08 ,  H04L9/00 ,  H04L9/065 ,  H04L2209/12 ,  Y02E10/541

摘要： Disclosed is a complementary resistor switch (3) comprising two outer contacts, between which two piezo- or ferroelectric layers (11a and 11b) having an inner common contact are situated. At least one region (11′, 11″) of the layers is modified, either the outer contacts are rectifying (S) and the inner contact is non-rectifying (O), or vice versa, the modified regions are formed at the rectifying contacts, the layers have different strain-dependent structural phases with different band gaps and/or different polarization charges, and the electrical conductivity of the layers is different. Also disclosed are a connectable resistor structure having at least one Schottky contact at two adjoining piezo- or ferroelectric layers, a polycrystalline piezo- or ferroelectric layer comprising modified crystallites, and a method and circuits for encrypting and decrypting a bit sequence.

摘要翻译： 公开了一种互补电阻器开关（3），其包括两个外部触点，在其间位于具有内部公共触点的两个压电层或铁电层（11a和11b）之间。 这些层的至少一个区域（11'，11“）被修改，外部触头被整流（S），内部触点是非整流（O），反之亦然，修正区域形成在整流 接触，这些层具有不同的带隙和/或不同极化电荷的不同的应变依赖结构相，并且层的导电性不同。 还公开了一种可连接的电阻器结构，其在两个相邻的压电或铁电层具有至少一个肖特基接触，包含经修改的微晶的多晶压电或铁电层，以及用于加密和解密位序列的方法和电路。

公开(公告)号：US09379100B2

公开(公告)日：2016-06-28

申请号：US14953319

申请日：2015-11-28

申请人： Renesas Electronics Corporation

发明人： Kazuo Sakamoto ,  Naozumi Morino ,  Kazuo Tanaka ,  Hiroyasu Ishizuka

IPC分类号： H03K19/0175 ,  H01L27/02 ,  H01L27/118

CPC分类号： H01L27/0288 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/11898 ,  H01L2027/11875 ,  H01L2224/05554 ,  H03K19/0175 ,  H03K19/08

摘要： A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

公开(公告)号：US09319048B2

公开(公告)日：2016-04-19

申请号：US14608333

申请日：2015-01-29

申请人： MARVELL WORLD TRADE LTD

发明人： Elad Lifshitz

IPC分类号： H03K21/02 ,  H03K19/08 ,  H03K19/21 ,  H03K5/19

CPC分类号： H03K21/026 ,  H03K5/19 ,  H03K19/08 ,  H03K19/21

摘要： Aspects of the disclosure provide a circuit including a logic circuit. The logic circuit is configured to operate without inputs from a first clock signal. The logic circuit is further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry driven by the first clock signal, and a second pattern provided by a second circuitry driven by the first clock signal.

摘要翻译： 本公开的方面提供了包括逻辑电路的电路。 逻辑电路被配置为在没有来自第一时钟信号的输入的情况下操作。 逻辑电路还被配置为对第一时钟信号进行分频，以基于由第一时钟信号驱动的第一电路提供的第一模式的逻辑组合和由第二电路提供的第二模式来产生第二时钟信号 由第一个时钟信号驱动。

公开(公告)号：US09319047B2

公开(公告)日：2016-04-19

申请号：US14573677

申请日：2014-12-17

申请人： UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.

发明人： Sumit Kumar Jha ,  Dilia E. Rodriguez ,  Joseph E. Van Nostrand ,  Alvaro Velasquez

IPC分类号： H03K19/0175 ,  H03K19/08 ,  H03K19/173

CPC分类号： H03K19/017581 ,  H03K19/08

摘要： Memristor-based nano-crossbar computing is a revolutionary computing paradigm that does away with the traditional Von Neumann architectural separation of memory and computation units. The computation of Boolean formulas using memristor circuits has been a subject of several recent investigations. Crossbar computing, in general, has also been a topic of active interest, but sneak paths have posed a hurdle in the design of pervasive general-purpose crossbar computing paradigms. Various embodiments are disclosed which demonstrate that sneak paths in nano-crossbar computing can be exploited to design a Boolean-formula evaluation strategy. Such nano-crossbar designs are also an effective approach for synthesizing high performance customized arithmetic and logic circuits.

摘要翻译： 基于忆阻器的纳米交叉计算是一种革命性的计算范式，它消除了传统的冯诺依曼建筑分离存储器和计算单元。 使用忆阻器电路的布尔公式的计算已经成为最近几项调查的主题。 一般来说，横杠计算也是一个积极兴趣的话题，但潜行路径在设计普遍的通用横杠计算范式方面构成了一个障碍。 公开了各种实施例，其示出了可以利用纳米交叉计算中的潜行路径来设计布尔公式评估策略。 这种纳米交叉设计也是合成高性能定制的算术和逻辑电路的有效方法。

公开(公告)号：US09312856B2

公开(公告)日：2016-04-12

申请号：US14146017

申请日：2014-01-02

申请人： National Tsing Hua University

发明人： Meng-Fan Chang ,  Tsung-Hsien Huang ,  Pei-Yuan Li

IPC分类号： H03K19/003 ,  H03K19/08 ,  H03K19/00

CPC分类号： H03K19/0008 ,  H03K19/003 ,  H03K19/08

摘要： A method for 3D voltage type TSV signal transmission, comprising transmitting a full swing signal of data with a first voltage through TSVs for each one of a plurality of slave devices to determine a transmission time required for data transmission to a master device. Then, full swing signal is sensed by the master device for reduce the first voltage to be a small swing signal with lower voltage. Logic “0” signals or logic “1” signals with the lower voltage are transmitted through the TSVs by the plurality of slave devices. It is sharing charge and balancing voltage level to a mean value for the logic “1” signals or the logic “0” signals by the master device.

摘要翻译： 一种用于3D电压型TSV信号传输的方法，包括通过针对多个从设备中的每一个的TSV为第一电压发送数据的全摆幅信号，以确定数据传输到主设备所需的传输时间。 然后，主控装置检测全速信号，以将第一电压降低为具有较低电压的小摆动信号。 具有较低电压的逻辑“0”信号或逻辑“1”信号通过多个从设备的TSV传输。 它将电荷和平衡电压电平分配给主器件的逻辑“1”信号或逻辑“0”信号的平均值。

公开(公告)号：US20160079231A1

公开(公告)日：2016-03-17

申请号：US14953319

申请日：2015-11-28

申请人： Renesas Electronics Corporation

发明人： Kazuo Sakamoto ,  Naozumi Morino ,  Kazuo Tanaka ,  Hiroyasu Ishizuka

IPC分类号： H01L27/02 ,  H01L27/118

CPC分类号： H01L27/0288 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/11898 ,  H01L2027/11875 ,  H01L2224/05554 ,  H03K19/0175 ,  H03K19/08

摘要： A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

公开(公告)号：US09231591B1

公开(公告)日：2016-01-05

申请号：US14568899

申请日：2014-12-12

申请人： Xilinx, Inc.

发明人： Austin H. Lesea

IPC分类号： H03K19/173 ,  H03K19/00 ,  H03K19/08

CPC分类号： H03K19/0016 ,  G06F1/28 ,  G06F1/3296 ,  G06F11/3062 ,  H03K3/0375 ,  H03K19/08 ,  Y02D10/172

摘要： An apparatus includes a first programmable circuit block including a plurality of programmable circuit elements. The plurality of programmable circuit elements include a hardwired, instrumented memory element. The instrumented memory element includes a first flip-flop configured to receive a data signal, a delay circuit configured to generate a delayed version of the data signal, and a second flip-flop identical to the first flip-flop and configured to receive the delayed version of the data signal. The instrumented memory element also may include a comparator configured to compare an output signal from the first flip-flop and an output signal from the second flip-flop and an error signal generator. The error signal generator is configured to generate an error signal responsive to a mismatch of bits between the output signal from the first flip-flop and the output signal from the second flip-flop.

摘要翻译： 一种装置包括包括多个可编程电路元件的第一可编程电路块。 多个可编程电路元件包括硬接线的仪表存储元件。 仪表存储元件包括被配置为接收数据信号的第一触发器，被配置为产生数据信号的延迟版本的延迟电路，以及与第一触发器相同的第二触发器，并且被配置为接收延迟的 版本的数据信号。 仪表存储元件还可以包括比较器，其被配置为比较来自第一触发器的输出信号和来自第二触发器的输出信号和误差信号发生器。 误差信号发生器被配置为响应于来自第一触发器的输出信号和来自第二触发器的输出信号之间的位的失配而产生误差信号。

公开(公告)号：US20150364682A1

公开(公告)日：2015-12-17

申请号：US14761319

申请日：2014-01-16

申请人： HELMHOLTZ-ZENTRUM DRESDEN-ROSSENDORF E.V.

发明人： Tiangui YOU ,  Heidemarie SCHMIDT ,  Nan DU ,  Danilo BUERGER ,  Ilona SKORUPA

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： H01L45/147 ,  G09C1/00 ,  G11C13/0007 ,  H01L27/2472 ,  H01L31/0749 ,  H01L45/065 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1641 ,  H01L45/165 ,  H03K19/08 ,  H04L9/00 ,  H04L9/065 ,  H04L2209/12 ,  Y02E10/541

摘要： Disclosed is a complementary resistor switch (3) comprising two outer contacts, between which two piezo- or ferroelectric layers (11a and 11b) having an inner common contact are situated. At least one region (11′, 11″) of the layers is modified, either the outer contacts are rectifying (S) and the inner contact is non-rectifying (0), or vice versa, the modified regions are formed at the rectifying contacts, the layers have different strain-dependent structural phases with different band gaps and/or different polarization charges, and the electrical conductivity of the layers is different. Also disclosed are a connectable resistor structure having at least one Schottky contact at two adjoining piezo- or ferroelectric layers, a polycrystalline piezo- or ferroelectric layer comprising modified crystallites, and a method and circuits for encrypting and decrypting a bit sequence.

摘要翻译： 公开了一种互补电阻器开关（3），其包括两个外部触点，在其间位于具有内部公共触点的两个压电层或铁电层（11a和11b）之间。 这些层的至少一个区域（11'，11“）被修改，外部触点是整流（S），内部触点是非整流（0），反之亦然，修正区域形成在整流 接触，这些层具有不同的带隙和/或不同极化电荷的不同的应变依赖结构相，并且层的导电性不同。 还公开了一种可连接的电阻器结构，其在两个相邻的压电或铁电层具有至少一个肖特基接触，包含经修改的微晶的多晶压电或铁电层，以及用于加密和解密位序列的方法和电路。