公开(公告)号：US10763426B2

公开(公告)日：2020-09-01

申请号：US16552169

申请日：2019-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L23/538 ,  H01L43/12 ,  H01L27/22 ,  H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L43/08

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US20190386204A1

公开(公告)日：2019-12-19

申请号：US16552169

申请日：2019-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L23/538 ,  H01L43/12

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US09842850B2

公开(公告)日：2017-12-12

申请号：US14983686

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  I-Ching Chen

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/115 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/32115 ,  H01L21/32133 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. The logic gate is arranged within a high κ dielectric layer. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate. The control transistor further comprises a charge trapping layer underlying the control gate. The control and select gates are a first material, and the logic gate is a second material. A high-κ-last method for manufacturing the IC is also provided.

公开(公告)号：US20170194333A1

公开(公告)日：2017-07-06

申请号：US14983682

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  I-Ching Chen

IPC: H01L27/115 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/321 ,  H03K19/08 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/32115 ,  H01L21/32133 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833 ,  H03K19/08

Abstract: An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high κ dielectric layers. A high-κ-last method for manufacturing the IC is also provided.

公开(公告)号：US11201281B2

公开(公告)日：2021-12-14

申请号：US16939583

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L23/538 ,  H01L43/12 ,  H01L27/22 ,  H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L43/08

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US10158072B1

公开(公告)日：2018-12-18

申请号：US15663671

申请日：2017-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jen-Sheng Yang ,  Wen-Ting Chu ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Yu-Wen Liao ,  Hsia-Wei Chen ,  I-Ching Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L45/00 ,  H01L27/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.

公开(公告)号：US10566519B2

公开(公告)日：2020-02-18

申请号：US15823012

申请日：2017-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L23/538 ,  H01L43/12 ,  H01L27/22 ,  H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L43/08

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US20190058109A1

公开(公告)日：2019-02-21

申请号：US15823012

申请日：2017-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L23/538

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US09754955B2

公开(公告)日：2017-09-05

申请号：US14983682

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  I-Ching Chen

IPC: H01L21/28 ,  H01L21/31 ,  H01L27/1157 ,  H03K19/08 ,  H01L27/11573 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/51

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/32115 ,  H01L21/32133 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833 ,  H03K19/08

Abstract: An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high κ dielectric layers. A high-κ-last method for manufacturing the IC is also provided.

公开(公告)号：US20170194334A1

公开(公告)日：2017-07-06

申请号：US14983686

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  I-Ching Chen

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/51 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/32115 ,  H01L21/32133 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. The logic gate is arranged within a high κ dielectric layer. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate. The control transistor further comprises a charge trapping layer underlying the control gate. The control and select gates are a first material, and the logic gate is a second material. A high-κ-last method for manufacturing the IC is also provided.