Invention Grant
- Patent Title: High-K-last manufacturing process for embedded memory with metal-oxide-nitride-oxide-silicon (MONOS) memory cells
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Application No.: US14983682Application Date: 2015-12-30
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Publication No.: US09754955B2Publication Date: 2017-09-05
- Inventor: Wei Cheng Wu , I-Ching Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/31 ; H01L27/1157 ; H03K19/08 ; H01L27/11573 ; H01L29/49 ; H01L29/66 ; H01L21/3213 ; H01L21/321 ; H01L29/51

Abstract:
An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high κ dielectric layers. A high-κ-last method for manufacturing the IC is also provided.
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