High-K-last manufacturing process for embedded memory with metal-oxide-nitride-oxide-silicon (MONOS) memory cells
Abstract:
An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high κ dielectric layers. A high-κ-last method for manufacturing the IC is also provided.
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