公开(公告)号：US20240339992A1

公开(公告)日：2024-10-10

申请号：US18202671

申请日：2023-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mitesh GOYAL ,  Hareharan NAGARAJAN ,  Abhishek GHOSH ,  CHIRANSHU BANTHIA

IPC: H03K3/3562 ,  G01R31/3185 ,  H03K3/012

CPC classification number: H03K3/35625 ,  G01R31/318544 ,  G01R31/318594 ,  H03K3/012

Abstract: A multibit flip flop is provided. The multibit flip flop includes: a first stage one-bit flip flop; and a second stage one-bit flip flop, wherein the first stage one-bit flip flop and the second stage one-bit flip flop are configured to share a common clock signal. The first stage one-bit flip flop and the second stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner. The first stage one-bit flip flop is further configured to provide a scan output signal based on a scan input signal provided at an input port of the first stage one-bit flip flop. The second stage one-bit flip flop is further configured to provide a scan final output signal based on the scan output signal that is provided at an input port of the second stage one-bit flip flop.