公开(公告)号：US11217308B1

公开(公告)日：2022-01-04

申请号：US16993795

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Mattia Robustelli ,  Innocenzo Tortorelli ,  Richard K. Dodge

IPC: G11C16/04 ,  G11C13/00

Abstract: The present disclosure includes apparatuses and methods for programming memory cells using asymmetric current pulses. An embodiment includes a memory having a plurality of self-selecting memory cells, and circuitry configured to program a self-selecting memory cell of the memory by applying a first current pulse or a second current pulse to the self-selecting memory cell, wherein the first current pulse is applied for a longer amount of time than the second current pulse and the first current pulse has a lower amplitude than the second current pulse.

公开(公告)号：US11205465B2

公开(公告)日：2021-12-21

申请号：US16694133

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Richard K. Dodge ,  Timothy C. Langtry

IPC: G11C8/10 ,  G11C7/10 ,  G11C8/16 ,  G11C5/06 ,  G11C13/00 ,  G11C8/14 ,  G11C7/18 ,  G11C5/02

Abstract: In an example, an apparatus includes a memory array in a first region and decode circuitry in a second region separate from a semiconductor. The decode circuitry is coupled to an access line in the memory array.

公开(公告)号：US11942183B2

公开(公告)日：2024-03-26

申请号：US17502481

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/1051

Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

公开(公告)号：US11869588B2

公开(公告)日：2024-01-09

申请号：US17727493

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Hernan A Castro ,  Jeremy M. Hirst ,  Shanky K. Jain ,  Richard K. Dodge ,  William A. Melton

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/71

Abstract: The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.

公开(公告)号：US20220075817A1

公开(公告)日：2022-03-10

申请号：US17526121

申请日：2021-11-15

Applicant: Micron Technology, Inc.

Inventor： Jeremy M. Hirst ,  Shanky K. Jain ,  Hernan A. Castro ,  Richard K. Dodge ,  William A. Melton

IPC: G06F16/587 ,  G06F16/21

Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.

公开(公告)号：US20190066743A1

公开(公告)日：2019-02-28

申请号：US15689017

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Richard K. Dodge ,  Timothy C. Langtry

IPC: G11C8/10 ,  G11C5/06 ,  G11C8/16 ,  G11C7/10

Abstract: In an example, an apparatus includes a memory array in a first region and decode circuitry in a second region separate from a semiconductor. The decode circuitry is coupled to an access line in the memory array.

公开(公告)号：US20220246210A1

公开(公告)日：2022-08-04

申请号：US17727493

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Jeremy M. Hirst ,  Shanky K. Jain ,  Richard K. Dodge ,  William A. Melton

IPC: G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.

公开(公告)号：US11315633B2

公开(公告)日：2022-04-26

申请号：US16729731

申请日：2019-12-30

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Jeremy M. Hirst ,  Shanky K. Jain ,  Richard K. Dodge ,  William A. Melton

IPC: G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.

公开(公告)号：US20220101899A1

公开(公告)日：2022-03-31

申请号：US17550668

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Richard K. Dodge ,  Timothy C. Langtry

IPC: G11C8/10 ,  G11C7/10 ,  G11C8/16 ,  G11C5/06 ,  G11C13/00 ,  G11C8/14 ,  G11C7/18 ,  G11C5/02

Abstract: In an example, an apparatus includes a memory array in a first region and decode circuitry in a second region separate from a semiconductor. The decode circuitry is coupled to an access line in the memory array.

公开(公告)号：US11177009B2

公开(公告)日：2021-11-16

申请号：US16729787

申请日：2019-12-30

Applicant: Micron Technology, Inc.

Inventor： Jeremy M. Hirst ,  Shanky K. Jain ,  Hernan A. Castro ,  Richard K. Dodge ,  William A. Melton

IPC: G11C8/00 ,  G11C16/34 ,  G11C16/26 ,  G11C16/12

Abstract: The present provision includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.