公开(公告)号：US20250031386A1

公开(公告)日：2025-01-23

申请号：US18777870

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Raghukiran Sreeramaneni ,  Nevil N. Gajera

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

Abstract: High-bandwidth memory (HBM) devices and associated systems and methods are disclosed herein. In some embodiments, the HBM devices include a first die, a plurality of second dies carried by a signal routing region of the first die, and active through substrate vias (TSVs) positioned within a footprint of the signal routing region. The active TSVs extend from a first metallization layer in the first die to a second metallization layer in an uppermost memory die. The HBM devices also include a cooling network configured to transport heat away from the first die. For example, the cooling network can include a thermally conductive layer carried by a thermal region of the first die and cooling TSVs in contact with the thermally conductive layer. The thermally conductive TSVs extend from the thermally conductive layer to an elevation at or above a top surface of the uppermost memory die.

公开(公告)号：US12080359B2

公开(公告)日：2024-09-03

申请号：US18189824

申请日：2023-03-24

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C7/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

公开(公告)号：US20240038301A1

公开(公告)日：2024-02-01

申请号：US17877613

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Francesco Mastroianni ,  Ferdinando Bedeschi ,  Nevil N. Gajera

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C2013/0057

Abstract: Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.

公开(公告)号：US11775431B2

公开(公告)日：2023-10-03

申请号：US17556891

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Sandeep Krishna Thirumala ,  Lingming Yang ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60 ,  G06F2212/72

Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.

公开(公告)号：US20230178167A1

公开(公告)日：2023-06-08

申请号：US17545335

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/20

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/1201 ,  G11C29/12005 ,  G11C29/20

Abstract: A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.

公开(公告)号：US11587635B2

公开(公告)日：2023-02-21

申请号：US17013089

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Nevil N. Gajera ,  Mingdong Cui ,  Fabio Pellizzer

IPC: G11C29/38 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.

公开(公告)号：US11545194B2

公开(公告)日：2023-01-03

申请号：US17306562

申请日：2021-05-03

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Jessica Chen ,  Lingming Yang

IPC: G11C7/10

Abstract: Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.

公开(公告)号：US20220392535A1

公开(公告)日：2022-12-08

申请号：US17336913

申请日：2021-06-02

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  Yen Chun Lee ,  Jessica Chen ,  Francesco Douglas Verna-Ketel

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08

Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.

公开(公告)号：US11475970B1

公开(公告)日：2022-10-18

申请号：US17337808

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Yen Chun Lee ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/34 ,  G11C29/12

Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.

公开(公告)号：US20220246221A1

公开(公告)日：2022-08-04

申请号：US17167618

申请日：2021-02-04

Applicant: Micron Technology, Inc.

Inventor： Nevil N. Gajera ,  Karthik Sarpatwari ,  Zhongyuan Lu

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.