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公开(公告)号：US11689394B2
公开(公告)日：2023-06-27
申请号：US16858156
申请日：2020-04-24
CPC分类号： H04L25/03267 , H04L25/03057 , H04L25/03949 , H04L25/06 , H04L25/062
摘要： A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.
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公开(公告)号：US20200252244A1
公开(公告)日：2020-08-06
申请号：US16858156
申请日：2020-04-24
摘要： A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.
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公开(公告)号：US20190356517A1
公开(公告)日：2019-11-21
申请号：US16526433
申请日：2019-07-30
IPC分类号： H04L25/03 , H04L25/49 , G11C7/10 , G11C11/4096 , G11C7/02
摘要： A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.
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公开(公告)号：US20190222445A1
公开(公告)日：2019-07-18
申请号：US16191169
申请日：2018-11-14
CPC分类号： H04L25/03057 , G11C7/02 , G11C7/1006 , G11C7/1063 , G11C11/4096 , G11C2207/107 , H04L25/4917
摘要： A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.
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公开(公告)号：US10348534B1
公开(公告)日：2019-07-09
申请号：US15864972
申请日：2018-01-08
CPC分类号： H04L25/061 , H04B1/16 , H04L25/03057
摘要： A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.
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公开(公告)号：US20190172546A1
公开(公告)日：2019-06-06
申请号：US15830281
申请日：2017-12-04
摘要： A method of operating an electronic device includes: generating a fuse read output based on reading a fuse cell at a predetermined data location in a fuse array, wherein the predetermined data location is configured to store predetermined data pattern; comparing the fuse read output to the predetermined data pattern; and generating a read-enable trigger based on the fuse read output matching the predetermined data pattern, wherein the read-enable trigger is for reading content stored in the fuse array and for broadcasting the content to circuits within the electronic device.
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公开(公告)号：US10218340B2
公开(公告)日：2019-02-26
申请号：US15853553
申请日：2017-12-22
IPC分类号： H03K5/134 , G11C11/4076 , G11C7/10 , G11C11/4093 , H03K5/00
摘要： The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.
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公开(公告)号：US20180123573A1
公开(公告)日：2018-05-03
申请号：US15853553
申请日：2017-12-22
IPC分类号： H03K5/134 , G11C11/4093 , G11C7/10 , G11C11/4076
CPC分类号： H03K5/134 , G11C7/1066 , G11C7/1093 , G11C11/4076 , G11C11/4093 , H03K2005/00052
摘要： The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.
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公开(公告)号：US20140040922A1
公开(公告)日：2014-02-06
申请号：US14046738
申请日：2013-10-04
IPC分类号： G06F9/44
CPC分类号： G06F9/4411 , G11C7/04 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C2207/2254
摘要： Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.
摘要翻译： 提供了驱动器系统和方法，例如包括识别驾驶员的过程角的那些; 并基于识别的过程角来配置驱动程序。 另外的实施例提供了一种方法，其包括检测驾驶员的过程角，基于检测到的过程角度来设置校准电路的参考电压，以及基于参考电压配置驾驶员。
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公开(公告)号：US20230403184A1
公开(公告)日：2023-12-14
申请号：US18214876
申请日：2023-06-27
CPC分类号： H04L25/03267 , H04L25/03949 , H04L25/06 , H04L25/062 , H04L25/03057
摘要： A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.
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