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公开(公告)号：US11775431B2
公开(公告)日：2023-10-03
申请号：US17556891
申请日：2021-12-20
发明人： Amitava Majumdar , Sandeep Krishna Thirumala , Lingming Yang , Karthik Sarpatwari , Nevil N. Gajera
IPC分类号： G06F12/08 , G06F12/0802
CPC分类号： G06F12/0802 , G06F2212/60 , G06F2212/72
摘要： This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.
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公开(公告)号：US11545194B2
公开(公告)日：2023-01-03
申请号：US17306562
申请日：2021-05-03
IPC分类号： G11C7/10
摘要： Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.
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公开(公告)号：US20220392535A1
公开(公告)日：2022-12-08
申请号：US17336913
申请日：2021-06-02
发明人： Karthik Sarpatwari , Nevil N. Gajera , Lingming Yang , Yen Chun Lee , Jessica Chen , Francesco Douglas Verna-Ketel
摘要： Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.
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公开(公告)号：US10964385B1
公开(公告)日：2021-03-30
申请号：US16684526
申请日：2019-11-14
发明人： Lingming Yang , Nevil Gajera , Karthik Sarpatwari
摘要： Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.
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5.发明授权公开(公告)号：US12032443B2
公开(公告)日：2024-07-09
申请号：US18156340
申请日：2023-01-18
CPC分类号： G06F11/1076 , G06F11/1004 , G06F13/4221
摘要： Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.
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6.发明授权公开(公告)号：US12013756B2
公开(公告)日：2024-06-18
申请号：US17894893
申请日：2022-08-24
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/0659 , G06F3/0689 , G06F11/1096
摘要： Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.
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公开(公告)号：US11782830B2
公开(公告)日：2023-10-10
申请号：US17556862
申请日：2021-12-20
发明人： Amitava Majumdar , Sandeep Krishna Thirumala , Lingming Yang , Karthik Sarpatwari , Nevil N. Gajera
IPC分类号： G06F12/00 , G06F12/0802
CPC分类号： G06F12/0802 , G06F2212/60 , G06F2212/72
摘要： This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.
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公开(公告)号：US20230236931A1
公开(公告)日：2023-07-27
申请号：US17894886
申请日：2022-08-24
CPC分类号： G06F11/1076 , G06F3/0689
摘要： Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.
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公开(公告)号：US11694747B2
公开(公告)日：2023-07-04
申请号：US17337806
申请日：2021-06-03
发明人： Lingming Yang , Xuan Anh Tran , Karthik Sarpatwari , Francesco Douglas Verna-Ketel , Jessica Chen , Nevil N. Gajera , Amitava Majumdar
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2013/0092
摘要： Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.
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公开(公告)号：US20230195624A1
公开(公告)日：2023-06-22
申请号：US17556891
申请日：2021-12-20
发明人： Amitava Majumdar , Sandeep Krishna Thirumala , Lingming Yang , Karthik Sarpatwari , Nevil N. Gajera
IPC分类号： G06F12/0802
CPC分类号： G06F12/0802 , G06F2212/60 , G06F2212/72
摘要： This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.
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