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公开(公告)号：US20240312525A1
公开(公告)日：2024-09-19
申请号：US18605169
申请日：2024-03-14
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Tomoko Ogura Iwasaki , Alessio Urbani , Justin Bates
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/08
Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. Following completion of the first drive operation, a second drive operation is executed to load second data into a second SGD associated with the second sub-block. Following completion of the second drive operation, a third drive operation is executed to re-load the first data into the first SGD.
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2.发明公开
公开(公告)号：US20240312537A1
公开(公告)日：2024-09-19
申请号：US18605237
申请日：2024-03-14
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Tomoko Ogura Iwasaki , Alessio Urbani , Justin Bates
CPC classification number: G11C16/3427 , G11C16/0433 , G11C16/102
Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. One or more program bias disturb mitigation operations are executed in association with a second drive operation to load second data into a second SGD associated with the second sub-block.
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公开(公告)号：US20240069749A1
公开(公告)日：2024-02-29
申请号：US18236087
申请日：2023-08-21
Applicant: Micron Technology, Inc.
Inventor： Augusto Benvenuti , Giovanni Maria Paolucci , Alessio Urbani , Gianpietro Carnevale , Aurelio Giancarlo Mauri
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679
Abstract: A memory access operation is initiated to read a set of target memory cells of a target wordline of the memory device. During the memory access operation, a read voltage level is caused to be applied to the target wordline. During the memory access operation, a first pass through voltage level is caused to be applied to a first wordline adjacent to the target wordline. During the memory access operation, a second pass through voltage is caused to be applied to a second wordline adjacent to the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level.
