公开(公告)号：US11636882B2

公开(公告)日：2023-04-25

申请号：US16667289

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Antonino Rigano

IPC: G11C5/00 ,  H01L27/108 ,  G11C5/06 ,  G11C5/02

Abstract: Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

公开(公告)号：US20220037533A1

公开(公告)日：2022-02-03

申请号：US17502546

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Antonino Rigano ,  Marcello Mariani

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/11592 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/108 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22 ,  G11C11/408 ,  H01L21/28 ,  H01L27/1159

Abstract: Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20180006087A1

公开(公告)日：2018-01-04

申请号：US15691576

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Antonino Rigano ,  Fabio Pellizzer ,  Gianfranco Capetti

IPC: H01L27/24 ,  H01L27/10 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

Abstract: Embodiments disclosed herein may relate to forming a base contact layout in a memory device.

公开(公告)号：US11888068B2

公开(公告)日：2024-01-30

申请号：US17502546

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Antonino Rigano ,  Marcello Mariani

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22 ,  G11C11/408 ,  H01L21/28 ,  H10B12/00 ,  H10B51/30 ,  H10B51/40 ,  H10B53/30 ,  H10B53/40

CPC classification number: H01L29/78642 ,  G11C11/2257 ,  G11C11/4085 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1222 ,  H01L27/1255 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/66742 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78651 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/50 ,  H10B51/30 ,  H10B51/40 ,  H10B53/30 ,  H10B53/40

Abstract: Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11877438B2

公开(公告)日：2024-01-16

申请号：US18076888

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Antonino Rigano

IPC: H01L21/00 ,  H10B12/00 ,  G11C11/22 ,  H01L29/78 ,  H10B53/30 ,  H10B53/40

CPC classification number: H10B12/34 ,  G11C11/221 ,  H01L29/7827 ,  H10B12/0383 ,  H10B53/30 ,  H10B53/40

Abstract: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.

公开(公告)号：US11049769B2

公开(公告)日：2021-06-29

申请号：US16111004

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Antonino Rigano ,  Roberto Somaschini

IPC: H01L21/768 ,  H01L45/00 ,  H01L27/24 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

公开(公告)号：US20210036162A1

公开(公告)日：2021-02-04

申请号：US16526074

申请日：2019-07-30

Applicant: Micron Technology, Inc.

Inventor： Antonino Rigano ,  Marcello Mariani

IPC: H01L29/786 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/108 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22 ,  G11C11/408 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US09548447B2

公开(公告)日：2017-01-17

申请号：US14927316

申请日：2015-10-29

Applicant: Micron Technology, Inc.

Inventor： Antonino Rigano

IPC: H01L29/06 ,  H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1691

Abstract: Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another. Some embodiments include methods of forming repeating structures. A pattern is formed which includes a lattice of intersecting wavy lines and a box surrounding the lattice. The pattern has a plurality of openings extending therethrough. A liner material is along sidewalls of the openings. The liner material and the pattern are sliced along a row direction and a column direction substantially orthogonal to the row direction. Such slicing subdivides the liner material into a plurality of plates. The plates are within an array comprising columns and rows. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another.

Abstract translation: 一些实施例包括具有穿过多个节点的重复板阵列的集成存储器。 阵列包括行和列。 沿着各列和各行的板在彼此基本正交的两个取向之间交替。 一些实施方案包括形成重复结构的方法。 形成图案，其包括相交的波浪线的格子和围绕格子的盒子。 该图案具有贯穿其中的多个开口。 衬垫材料沿着开口的侧壁。 衬垫材料和图案沿着与行方向大致正交的行方向和列方向切片。 这种切片将衬垫材料细分成多个板。 这些板在包括列和行的阵列内。 沿着各列和各行的板在彼此基本正交的两个取向之间交替。

公开(公告)号：US09520554B2

公开(公告)日：2016-12-13

申请号：US13783884

申请日：2013-03-04

Applicant: Micron Technology, Inc.

Inventor： Antonino Rigano ,  Fabio Pellizzer

IPC: G11C11/00 ,  G11C11/36 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/1691 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/124 ,  H01L45/128 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

Abstract: Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.

Abstract translation: 本文公开了夹紧元件，存储器，装置及其形成方法。 示例性存储器可以包括存储器单元阵列和多个钳位元件。 多个钳位元件的钳位元件可以包括相对于存储器单元阵列的位线或字线中的至少一个非正交形成的单元结构，并且可以被配置为控制相应位线的电压 。

公开(公告)号：US20150295173A1

公开(公告)日：2015-10-15

申请号：US14250114

申请日：2014-04-10

Applicant: Micron Technology, Inc.

Inventor： Antonino Rigano

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1691

Abstract: Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another. Some embodiments include methods of forming repeating structures. A pattern is formed which includes a lattice of intersecting wavy lines and a box surrounding the lattice. The pattern has a plurality of openings extending therethrough. A liner material is along sidewalls of the openings. The liner material and the pattern are sliced along a row direction and a column direction substantially orthogonal to the row direction. Such slicing subdivides the liner material into a plurality of plates. The plates are within an array comprising columns and rows. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another.

Abstract translation: 一些实施例包括具有穿过多个节点的重复板阵列的集成存储器。 阵列包括行和列。 沿着各列和各行的板在彼此基本正交的两个取向之间交替。 一些实施方案包括形成重复结构的方法。 形成图案，其包括相交的波浪线的格子和围绕格子的盒子。 该图案具有贯穿其中的多个开口。 衬垫材料沿着开口的侧壁。 衬垫材料和图案沿着与行方向大致正交的行方向和列方向切片。 这种切片将衬垫材料细分成多个板。 这些板在包括列和行的阵列内。 沿着各列和各行的板在彼此基本正交的两个取向之间交替。