知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.013 seconds)

    Multi-pass programming operation sequence in a memory device
    1.
    发明授权
    Multi-pass programming operation sequence in a memory device 有权

    公开(公告)号：US12046279B2

    公开(公告)日：2024-07-23

    申请号：US17751179

    申请日：2022-05-23

    Applicant: SanDisk Technologies LLC

    Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

    Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

    MULTI-PASS PROGRAMMING OPERATION SEQUENCE IN A MEMORY DEVICE
    2.
    发明公开
    MULTI-PASS PROGRAMMING OPERATION SEQUENCE IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230377643A1

    公开(公告)日：2023-11-23

    申请号：US17751179

    申请日：2022-05-23

    Applicant: SanDisk Technologies LLC

    Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10

    CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10

    Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

    PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO
    3.
    发明公开
    PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO 审中-公开

    公开(公告)号：US20240242764A1

    公开(公告)日：2024-07-18

    申请号：US18222735

    申请日：2023-07-17

    Applicant: SanDisk Technologies LLC

    Inventor： Huiwen Xu ,  Deepanshu Dutta ,  Jia Li ,  Bo Lei ,  Ken Oowada

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

    CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08

    Abstract: The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.

    VARIABLE PROGRAMMING VOLTAGE STEP SIZE CONTROL DURING PROGRAMMING OF A MEMORY DEVICE
    5.
    发明申请
    VARIABLE PROGRAMMING VOLTAGE STEP SIZE CONTROL DURING PROGRAMMING OF A MEMORY DEVICE 有权

    公开(公告)号：US20230124371A1

    公开(公告)日：2023-04-20

    申请号：US17502398

    申请日：2021-10-15

    Applicant: SanDisk Technologies LLC

    Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04

    Abstract: The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.

    Reduced verify scheme during programming based on spacing between verify levels
    7.
    发明授权
    Reduced verify scheme during programming based on spacing between verify levels 有权

    公开(公告)号：US11328780B1

    公开(公告)日：2022-05-10

    申请号：US17116579

    申请日：2020-12-09

    Applicant: SanDisk Technologies LLC

    Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08

    Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device in which groups of memory cells are programmed from checkpoint states to respective data states. In a first program pass, groups of memory cells are programmed to respective checkpoint states with verify tests. Each checkpoint state is associated with a set of data states. In a second program pass, the memory cells are programmed closer to their assigned data state with a specified number of program pulses. In a third program pass, the memory cells are programmed to their assigned data state by applying program pulses and performing verify tests. The number of checkpoint states and the number of data states associated with each checkpoint state can be optimized based on a spacing between the verify voltages of the data states.

    DYNAMIC SENSE NODE VOLTAGE TO COMPENSATE FOR VARIANCES WHEN SENSING THRESHOLD VOLTAGES OF MEMORY CELLS
    10.
    发明申请
    DYNAMIC SENSE NODE VOLTAGE TO COMPENSATE FOR VARIANCES WHEN SENSING THRESHOLD VOLTAGES OF MEMORY CELLS 有权

    公开(公告)号：US20220246208A1

    公开(公告)日：2022-08-04

    申请号：US17166612

    申请日：2021-02-03

    Applicant: SanDisk Technologies LLC

    Inventor： Huiwen Xu ,  Bo Lei ,  Jun Wan

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00

    Abstract: Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors.

Patent Agency Ranking