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    POWER SAVING AND FAST READ SEQUENCE FOR NON-VOLATILE MEMORY
    1.
    发明申请
    POWER SAVING AND FAST READ SEQUENCE FOR NON-VOLATILE MEMORY 有权

    公开(公告)号：US20220208276A1

    公开(公告)日：2022-06-30

    申请号：US17135071

    申请日：2020-12-28

    Applicant: SanDisk Technologies LLC

    Inventor： Jianzhi Wu ,  Jia Li ,  Yanjie Wang

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.

    Dynamic read table generation
    2.
    发明授权
    Dynamic read table generation 有权

    公开(公告)号：US10558381B2

    公开(公告)日：2020-02-11

    申请号：US15381104

    申请日：2016-12-16

    Applicant: SanDisk Technologies LLC

    Inventor： Henry Chin ,  Sateesh Desireddi ,  Dana Lee ,  Ashwin D T ,  Harshul Gupta ,  Parth Amin ,  Jia Li

    IPC: G06F3/06

    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.

    PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO
    4.
    发明公开
    PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO 审中-公开

    公开(公告)号：US20240242764A1

    公开(公告)日：2024-07-18

    申请号：US18222735

    申请日：2023-07-17

    Applicant: SanDisk Technologies LLC

    Inventor： Huiwen Xu ,  Deepanshu Dutta ,  Jia Li ,  Bo Lei ,  Ken Oowada

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

    CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08

    Abstract: The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.

    Power saving and fast read sequence for non-volatile memory
    6.
    发明授权
    Power saving and fast read sequence for non-volatile memory 有权

    公开(公告)号：US11721397B2

    公开(公告)日：2023-08-08

    申请号：US17135071

    申请日：2020-12-28

    Applicant: SanDisk Technologies LLC

    Inventor： Jianzhi Wu ,  Jia Li ,  Yanjie Wang

    IPC: G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/08

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C11/5671

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.

    MODIFYING PROGRAM AND ERASE PARAMETERS FOR SINGLE-BIT MEMORY CELLS TO IMPROVE SINGLE-BIT/MULTI-BIT HYBRID RATIO
    9.
    发明申请
    MODIFYING PROGRAM AND ERASE PARAMETERS FOR SINGLE-BIT MEMORY CELLS TO IMPROVE SINGLE-BIT/MULTI-BIT HYBRID RATIO 有权

    公开(公告)号：US20230058038A1

    公开(公告)日：2023-02-23

    申请号：US17404217

    申请日：2021-08-17

    Applicant: SanDisk Technologies LLC

    Inventor： Abu Naser Zainuddin ,  Jia Li ,  Jiahui Yuan ,  Bo Lei

    IPC: G11C16/16 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04

    Abstract: Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.

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