- 专利标题: ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES
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申请号: US18771393申请日: 2024-07-12
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公开(公告)号: US20240363190A1公开(公告)日: 2024-10-31
- 发明人: Li-Te Chang , Yu-Chung Lien , Murong Lang , Zhenming Zhou , Michael G. Miller
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 主分类号: G11C29/52
- IPC分类号: G11C29/52 ; G11C16/08 ; G11C16/10 ; G11C16/34
摘要:
An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.
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