公开(公告)号：US11966625B2

公开(公告)日：2024-04-23

申请号：US17722850

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Guyeon Han ,  Sangwon Park ,  Jinkyu Kang ,  Raeyoung Lee ,  Jaeduk Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Provided are a memory device storing setting data and a memory system including the same. The memory device may include a cell array including a plurality of cell blocks, each including a plurality of pages, and a control logic that controls a program and read operation on the cell array, wherein at least one page of the cell array stores information data read (IDR) data including information related to a setting operation of the memory device, at least one other page of the cell array stores replica IDR data including inverted bit values of the IDR data, and the control logic controls a recovery operation for repairing errors in the IDR data by reading the replica IDR data when a read fail of the IDR data occurs.

公开(公告)号：US20220399401A1

公开(公告)日：2022-12-15

申请号：US17826944

申请日：2022-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongseok Kwon ,  Youngsik Rho ,  Sangwon Park ,  Sungwhan Seo ,  Dongkyu Lee ,  Jaeyong Jeong

IPC: H01L27/24

Abstract: A memory device including a first substrate extending in a first direction and a second direction perpendicular to the first direction, the first substrate including a memory cell region and a first peripheral circuit region, and a second substrate, including a second peripheral circuit region, extending in the first and second direction, the second substrate overlapping the first substrate in a third direction perpendicular to the first and second direction. The memory device also including a memory cell array disposed in the memory cell region and including a plurality of vertical channel structures extending in the third direction, a peripheral circuit disposed in the second peripheral circuit region, and a resistor extending in the third direction through the first peripheral circuit region and the second peripheral circuit region. The resistor including a plurality of resistance contact structures overlapping the plurality of vertical channel structures in the first direction.

公开(公告)号：US11200002B2

公开(公告)日：2021-12-14

申请号：US16918310

申请日：2020-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US09214993B2

公开(公告)日：2015-12-15

申请号：US14201600

申请日：2014-03-07

Applicant: Samsung Electronics Co., Ltd. ,  INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

Inventor： Hyojin Lee ,  Chungyong Lee ,  Hoondong Nho ,  Younsun Kim ,  Juho Lee ,  Hyoungju Ji ,  Sangwon Park ,  Ilgyu Choi

IPC: H04B7/02 ,  H04B7/04 ,  H04B7/06

CPC classification number: H04B7/0456 ,  H04B7/0617 ,  H04B7/0619 ,  H04B7/0639 ,  H04B7/0658 ,  H04L25/0204 ,  H04L25/0228

Abstract: The present disclosure relates to a method and an apparatus for transmitting and receiving channel related information. A method of transmitting channel related information of a UE according to an embodiment of the present disclosure includes configuring a sub-channel corresponding to a part of a plurality of antennas of an eNB; acquiring a Channel Estimation Error (CEE) and a Precoding Matrix Indicator (PMI) corresponding to the sub-channel; and transmitting a Sub-channel Indicator (SI) indicating the sub-channel, according to the CEE and the PMI. In accordance with an embodiment of the present disclosure, the channel related information is efficiently transmitted and received in a system in which a plurality of antennas is used.

Abstract translation: 本公开涉及一种用于发送和接收信道相关信息的方法和装置。 根据本公开的实施例的发送UE的信道相关信息的方法包括配置与eNB的多个天线的一部分相对应的子信道; 获取对应于子信道的信道估计误差（CEE）和预编码矩阵指示符（PMI）; 以及根据CEE和PMI发送指示子信道的子信道指示符（SI）。 根据本公开的实施例，信道相关信息在其中使用多个天线的系统中被有效地发送和接收。

公开(公告)号：US20240420772A1

公开(公告)日：2024-12-19

申请号：US18512279

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon Park ,  Jooyong Park ,  Jaeha Park

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

Abstract: A nonvolatile memory device may include at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of sub-blocks arranged in the vertical direction, and each of the sub-blocks includes boundary word-lines adjacent to another sub-block and internal word-lines different from the boundary word-lines. The control circuit may be configured to control an erase operation by applying a pre-program voltage with a first individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, and by applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop.

公开(公告)号：US11709629B2

公开(公告)日：2023-07-25

申请号：US17455037

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H10B41/27 ,  H10B43/27

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US20220415408A1

公开(公告)日：2022-12-29

申请号：US17648311

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong PARK ,  Sangwon Park ,  Dongjin SHIN ,  Suchang Jeon ,  Seungyong CHOI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20

Abstract: A non-volatile memory device includes a meta area having a first region storing first initial data, and second regions storing second initial data, different from each other; a user area configured to store user data; an initialization register configured to store the first initial data or update the second initial data in whole or in part; and control logic configured to perform a read operation, a program operation, or an erase operation using the initial data stored in the initialization register.

公开(公告)号：US20210149598A1

公开(公告)日：2021-05-20

申请号：US16918310

申请日：2020-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US12190964B2

公开(公告)日：2025-01-07

申请号：US17750315

申请日：2022-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggi Hong ,  Chaehoon Kim ,  Sangwon Park ,  Jiho Cho

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.

公开(公告)号：US20240222202A1

公开(公告)日：2024-07-04

申请号：US18498194

申请日：2023-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon Park ,  Seunghak Park ,  Byeonghwan Son ,  Ayeong Cha

IPC: H01L21/66 ,  G01B11/06 ,  H01L21/67

CPC classification number: H01L22/26 ,  G01B11/06 ,  H01L21/67253 ,  H10B41/27

Abstract: A method of manufacturing a device includes forming a first layer on a first substrate, the first layer for measuring a thickness thereof; irradiating the first layer with first light having a first wavelength that passes into the first layer; sensing first reflected light reflected from a bottom surface of the first layer; irradiating the first layer with second light having a second wavelength shorter than the first wavelength that reflects from the first layer; sensing second reflected light reflected from an upper surface of the first layer; obtaining first data corresponding to a first positional coordinate in a vertical direction of the bottom surface of the first layer from the first reflected light; obtaining second data corresponding to a second positional coordinate in the vertical direction of the upper surface of the first layer from the second reflected light; and obtaining skew data representing a thickness of the first layer using the first and second data.