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公开(公告)号：US12057391B2
公开(公告)日：2024-08-06
申请号：US17933770
申请日：2022-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yohan Lee , Chaehoon Kim , Jaeduk Yu , Jiho Cho
IPC: H01L27/115 , H01L23/522 , H10B43/27
CPC classification number: H01L23/5226 , H10B43/27
Abstract: A semiconductor device includes a CSL driver on a substrate, a CSP on the CSL driver, a gate electrode structure on the CSP and including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, a memory channel structure on the CSP and extending through the gate electrode structure and is connected to the CSP, a first upper wiring structure contacting an upper surface of the CSP, a first through via extending through the CSP in the first direction and is electrically connected to the first upper wiring structure and the CSL driver but does not contact the CPS, and a dummy wiring structure contacting the upper surface of the CSP but is not electrically connected to the CSL driver.
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2.发明授权公开(公告)号：US12176046B2
公开(公告)日：2024-12-24
申请号：US17955858
申请日：2022-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yohan Lee , Sang-Wan Nam , Sang-Won Park , Jiho Cho , Eunhyang Park
Abstract: Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.
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公开(公告)号：US12190964B2
公开(公告)日：2025-01-07
申请号：US17750315
申请日：2022-05-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanggi Hong , Chaehoon Kim , Sangwon Park , Jiho Cho
Abstract: In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.
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4.发明授权公开(公告)号：US12062395B2
公开(公告)日：2024-08-13
申请号：US17750642
申请日：2022-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yohan Lee , Chaehoon Kim , Jungyun Yun , Jiho Cho , Sanggi Hong
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C11/5628 , G11C16/3445 , G11C16/3459
Abstract: A nonvolatile memory device includes a memory block and a control circuit. The memory block includes a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line. The control circuit adjusts a level of a high voltage applied to a gate of a pass transistor of a selected word-line such that a voltage difference between the high voltage and a program voltage applied to a drain of the pass transistor differs in at least a portion of a plurality of program loops based on a comparison of a number of the program loops and a reference number during a program operation on a target memory cells.
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Patent Agency Ranking
公开(公告)号：US11763879B2
公开(公告)日：2023-09-19
申请号：US17322065
申请日：2021-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoonjee Kim , Seungyeon Kim , Sangwan Nam , Hongsoo Jeon , Jiho Cho
IPC: G11C11/4097 , G11C5/06 , G11C11/4093 , G11C11/408 , G11C11/4099
CPC classification number: G11C11/4097 , G11C5/06 , G11C11/4085 , G11C11/4087 , G11C11/4093 , G11C11/4099
Abstract: A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.
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6.发明公开公开(公告)号：US20230146041A1
公开(公告)日：2023-05-11
申请号：US18052428
申请日：2022-11-03
Applicant: Samsung Electronics Co., Ltd.
IPC: G06F3/06
CPC classification number: G06F3/0607 , G06F3/064 , G06F3/0679 , G06F3/0653
Abstract: According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.
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7.发明授权公开(公告)号：US12147666B2
公开(公告)日：2024-11-19
申请号：US18052428
申请日：2022-11-03
Applicant: Samsung Electronics Co., Ltd.
IPC: G06F3/06
Abstract: According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.
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8.发明授权公开(公告)号：US12119046B2
公开(公告)日：2024-10-15
申请号：US18045541
申请日：2022-10-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeduk Yu , Yohan Lee , Yonghyuk Choi , Jiho Cho
IPC: G11C16/34 , G11C11/4074 , G11C11/408 , G11C11/4096
CPC classification number: G11C11/4085 , G11C11/4074 , G11C11/4096
Abstract: A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.
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公开(公告)号：US09805807B2
公开(公告)日：2017-10-31
申请号：US15003113
申请日：2016-01-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Cheon An Lee , Mu-Hui Park , Jiho Cho , Ji-Young Lee , Yoon-Hee Choi
CPC classification number: G11C16/16 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3427
Abstract: A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.
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