公开(公告)号：US20240096420A1

公开(公告)日：2024-03-21

申请号：US18522829

申请日：2023-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/349 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

公开(公告)号：US20240321361A1

公开(公告)日：2024-09-26

申请号：US18732377

申请日：2024-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE ,  KANG-BIN LEE

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

公开(公告)号：US20230170299A1

公开(公告)日：2023-06-01

申请号：US17979179

申请日：2022-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNG-MIN JOE ,  SANG SOO PARK ,  CHUNG-HO YU

IPC: H01L23/528 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26

CPC classification number: H01L23/528 ,  G11C16/26 ,  G11C16/0483 ,  H01L27/11582

Abstract: A memory device includes a substrate, a first cell string, second cell string, and third cell string, each connected to a first bit line and formed in a direction perpendicular to a top surface of the substrate, a first upper ground selection line connected to the first cell string, a second upper ground selection line separated from the first upper ground selection line and connected to the second and third cell strings, a first lower ground selection line connected to the first and second cell strings, and a second lower ground selection line separated from the first lower ground selection line and connected to the third cell string.

公开(公告)号：US20190267107A1

公开(公告)日：2019-08-29

申请号：US16257985

申请日：2019-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A method of operating a nonvolatile memory device includes: performing a first program operation by applying a first program voltage to a selected word line connected to a selected memory cell; performing a first verify operation by applying a verify voltage to the selected word line and applying a first word line voltage to at least one unselected word line; performing a second program operation by applying a second program voltage to the selected word line; and performing a second verify operation by applying a verify voltage to the selected word line and applying a second word line voltage to the at least one unselected word line, wherein at least one of the first word line voltage and the second word line voltage has a lower voltage level than a read voltage applied in a read operation of the nonvolatile memory device.

公开(公告)号：US20220068394A1

公开(公告)日：2022-03-03

申请号：US17524099

申请日：2021-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE ,  KANG-BIN LEE

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

公开(公告)号：US20200342942A1

公开(公告)日：2020-10-29

申请号：US16927100

申请日：2020-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE ,  Kang-Bin Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

公开(公告)号：US20190267092A1

公开(公告)日：2019-08-29

申请号：US16257768

申请日：2019-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE ,  Kang-Bin Lee

IPC: G11C16/10 ,  G11C11/4091 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C7/12 ,  G11C8/14

Abstract: A method of operating a memory device includes performing a first program operation on memory cells connected to a first word line among a plurality of word lines, performing the first program operation on memory cells connected to a second word line among the plurality of word lines, applying a turn-on voltage at a first level to the first and second word lines, applying a voltage at a level lower than the first level to a third word line among the plurality of word lines, performing a precharge operation on partial cell strings among a plurality of cell strings, and performing a second program operation on the memory cells connected to the first word line.

公开(公告)号：US20190096488A1

公开(公告)日：2019-03-28

申请号：US16135213

申请日：2018-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE ,  Seung-Jae Lee ,  Sun-gun Lee

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  G11C8/14 ,  H01L27/11582

Abstract: A method of programming a non-volatile memory device including a first memory block and a second memory block includes: performing a first program operation on a first memory cell in the first memory block and connected to a first word line of a first level with respect to a substrate; after the performing of the first program operation on the first memory cell, performing the first program operation on a second memory cell in the second memory block and connected to a second word line of the first level; and after the performing off the first program operation on the second memory cell, performing a second program operation on the first memory cell.

公开(公告)号：US20230240076A1

公开(公告)日：2023-07-27

申请号：US17985328

申请日：2022-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANG-LOK KIM ,  SANG SOO PARK ,  JUNG-JUNE PARK ,  SU CHANG JEON ,  SUNG-MIN JOE

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L25/065

CPC classification number: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L25/0655

Abstract: Disclosed are semiconductor devices and semiconductor packages. The semiconductor device comprises a semiconductor substrate that includes a stack region and a pad region, a peripheral circuit structure that includes a plurality of peripheral circuits on the semiconductor substrate, a cell array structure on the peripheral circuit structure, and a redistribution layer on the cell array structure and including a redistribution dielectric layer and a redistribution pattern on the redistribution dielectric layer. The redistribution dielectric layer covers an uppermost conductive pattern of the cell array structure. The redistribution pattern is connected to the uppermost conductive pattern. A thickness in a vertical direction of the redistribution layer on the pad region is greater than that of the redistribution layer on the stack region.

公开(公告)号：US20230197161A1

公开(公告)日：2023-06-22

申请号：US18173730

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE ,  Kang-Bin LEE

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/05 ,  H10B41/27 ,  H10B43/27 ,  H01L2924/14511 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.