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1.发明公开公开(公告)号：US20240071525A1
公开(公告)日：2024-02-29
申请号：US17895625
申请日：2022-08-25
CPC分类号： G11C16/3459 , G11C16/10
摘要： A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings and the strings comprise a plurality of blocks which comprise planes. A control means is configured to program the memory cells connected to one of the word lines and associated with one of the strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the planes in a smart verify operation. The control means concurrently programs at least some of the memory cells connected to each of the word lines in each of the planes in a program operation using the smart verify programming voltage individually acquired for each of the planes in the smart verify operation.
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公开(公告)号：US10748619B1
公开(公告)日：2020-08-18
申请号：US16406605
申请日：2019-05-08
发明人： Liang Li
IPC分类号： G11C16/04 , G11C16/08 , G11C11/56 , G11C16/16 , G11C7/10 , G11C16/26 , G11C16/34 , G11C16/24
摘要： Techniques are described for configuring a memory device with parameters for multiple operating modes including M-bit per cell and N-bit per cell operating modes. The parameters can be stored in ROM storage locations of the memory device and loaded into registers when powering on the memory device. The parameters can be accessed by a state machine based on command sequences receive from a controller. The command sequences can include one or more prefix commands which specify the operating mode, e.g., the number of bits per cell, commands which specify a type of an operation, and an address of memory cells on which the operation is to be performed. The state machine can easily switch between accessing parameters for different modes without the controller including the parameters in the command sequences.
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公开(公告)号：US11972817B2
公开(公告)日：2024-04-30
申请号：US17837903
申请日：2022-06-10
CPC分类号： G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/3404
摘要： A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.
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公开(公告)号：US11894077B2
公开(公告)日：2024-02-06
申请号：US17678584
申请日：2022-02-23
CPC分类号： G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/30
摘要： A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.
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5.发明公开公开(公告)号：US20230268015A1
公开(公告)日：2023-08-24
申请号：US17678584
申请日：2022-02-23
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/26 , G11C16/08 , G11C16/30
摘要： A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.
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公开(公告)号：US20230078456A1
公开(公告)日：2023-03-16
申请号：US17473183
申请日：2021-09-13
摘要： A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at least one memory cell of the selected word line to a last data state in at least one last data state programming loop. In response to both the total number of programming loops being less than a first predetermined threshold and the number of last data state programming loops being equal to a second predetermined threshold, the control circuitry automatically skips verify in a final programming loop.
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公开(公告)号：US11257835B2
公开(公告)日：2022-02-22
申请号：US16692027
申请日：2019-11-22
IPC分类号： H01L27/11565 , H01L27/11524 , H01L27/11556 , H01L27/11519 , H01L21/28 , H01L21/768 , H01L27/11582 , H01L23/522 , H01L23/528 , H01L27/1157
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, rows of memory openings vertically extending through the alternating stack, memory opening fill structures located within a first subset of the rows of memory openings, where each of the memory opening fill structures includes a respective memory film and a respective vertical semiconductor channel extending through an opening at a bottom portion of the respective memory film and contacting a respective underlying semiconductor material portion, and dummy memory opening fill structures located within a second subset of the rows of memory openings that do not belong the first subset, where each of the dummy memory opening fill structures includes a respective dummy memory film and a respective dummy vertical semiconductor channel that is electrically isolated from a respective underlying semiconductor material portion by a bottom portion of the respective dummy memory film.
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公开(公告)号：US20210398604A1
公开(公告)日：2021-12-23
申请号：US16914653
申请日：2020-06-29
摘要： A memory apparatus and method of operation is provided. The apparatus has blocks each including non-volatile storage elements. Each of the non-volatile storage elements stores a threshold voltage representative of an element data. The apparatus also includes one or more managing circuits configured to erase at least one of the blocks in an erase operation and program the element data in a program operation. The one or more managing circuits are also configured to proactively identify ones of the blocks as potential bad blocks and selectively apply stress to the ones of the blocks identified as the potential bad blocks and determine whether the potential bad blocks should be retired from the erase and program operations and put in a grown bad block pool or released to a normal block pool used for the erase and program operations based on a judgment after selectively applying the stress.
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公开(公告)号：US11901015B2
公开(公告)日：2024-02-13
申请号：US17572292
申请日：2022-01-10
摘要： The memory device includes a plurality of memory cell that arranged in an array, which includes a plurality of channels that are in electrical communication with a source line. The memory device also includes a controller that is configured to erase the memory cells in at least one erase pulse. During the at least one erase pulse, the controller is configured to drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick. The controller is then configured to reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse, including after the voltage of the source line has been reduced to the erase voltage Vera.
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10.发明公开公开(公告)号：US20230420053A1
公开(公告)日：2023-12-28
申请号：US17846452
申请日：2022-06-22
发明人： Xuan Tian , Henry Chin , Liang Li , Vincent Yin , Wei Zhao , Tony Zou
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/24 , G11C16/08 , G11C16/26 , G11C16/349 , G11C29/50004 , H01L27/11556
摘要： The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.
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